MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 224

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Arbiter and Bus Monitor
failure had caused a deadlock situation. For more information, see
Sequence.”
Figure 6-7
Table 6-8
6.2.8
The arbiter event response register (AERR) determines whether different error conditions cause interrupt
or reset request. Setting a bit defines the corresponding error condition to cause reset request; clearing a
bit defines the corresponding error condition to cause interrupt.
Table 6-9
6-10
Offset 0x20
Reset
0–31
0–25
Bits
Bits
26
27
Offset 0x1C
Reset
W
R
W
R
0
0
ADDR
describes AEADR fields.
Name
describes AERR field.
Name
ETEA
RES
shows the fields of AEADR.
—
Arbiter Event Response Register (AERR)
Address of the event reported in AEATR register. See
(AEATR),”
Write reserved, read = 0
Transfer error. Detection of transfer error by one of the slaves event response.
0 Detection of transfer error by one of the slaves causes interrupt.
1 Detection of transfer error by one of the slaves causes reset request.
Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes interrupt.
1 Transaction with reserved transfer type causes reset request.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 6-7. Arbiter Event Address Register (AEADR)
Figure 6-8. Arbiter Event Response Register (AERR)
for more information.
Table 6-8. AEADR Field Descriptions
Table 6-9. AERR Field Descriptions
—
All zeros
All zeros
ADDR
Description
Description
Section 6.2.6, “Arbiter Event Attributes Register
Figure 6-8
Section 6.4.2, “Error Handling
25
shows the fields of AERR.
ETEA RES ECW AO DTO ATO
26
27
Freescale Semiconductor
Access: User read/write
Access: User read/write
28
29
30
31
31