MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1116

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface
19.2
The SPI’s four wire interface consists of transmit, receive, clock, and slave select.
19.2.1
Table 19-1
19.2.2
Table 19-2
19-6
SPIMISO
SPIMOSI
SPIMISO
SPIMOSI
Signal
SPICLK
SPISEL
Name
External Signal Descriptions
lists signal properties.
describes the signals in detail.
Overview
Detailed Signal Descriptions
I/O
I/O Master input slave output
I/O Master output slave input
SPI slave select
Master input slave output
Master output slave input
Input/output serial clock connected to the other SPICLK
Meaning
Meaning
Timing
Timing
State
State
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
slave mode) is high
slave mode) is low
SPMODE)
SPMODE)
slave mode) is high
slave mode) is low
SPMODE)
SPMODE)
Table 19-2. Detailed Signal Descriptions
Function
Table 19-1. Signal Properties
Description
Reset
—
—
—
—
Required in open drain mode
Required in open drain mode
Required in open drain mode
Required in open drain mode
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