MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 817

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.5.2.3
PEX_CSB_STAT, shown in
When a transaction is initiated by the PCI Express DMA or PIO, the corresponding pending bit is set until
a response is received.
Table 14-95
14.5.3
The registers discussed in this section control PIO outbound transactions initiated by a CSB master.
Freescale Semiconductor
Offset 0x81C
Reset
Reset
31–25
23–17
15–9
Bits
7–1
24
16
8
0
W
W
R
R
31
15
WDMARP
OBPIORP
RDMARP
IBPIORP
Name
PCI Express Outbound PIO Registers
—
—
—
—
defines the bit field for PEX_CSB_STAT.
PCI Express CSB Bridge Status Register (PEX_CSB_STAT)
Figure 14-97. PCI Express CSB Bridge Status Register (PEX_CSB_STAT)
Reserved
Read DMA read transaction pending. Indicates whether a response is pending from the PCI Express
bus to a transfer by the read DMA engine.
0 No response pending
1 Response is pending
Reserved
Write DMA read transaction pending.Indicates whether a response is pending from the CSB bus to a
transfer from the write DMA engine.
0 No response pending
1 Response is pending
Reserved
PCI Express inbound PIO read transaction pending. Indicates whether a response is pending from the
CSB bus for an inbound transfer from the PCI Express bus
0 No response pending
1 Response is pending
Reserved
PCI Express outbound PIO read transaction pending. Indicates whether a response is pending from the
PCI Express bus for a transfer initiated on the CSB bus.
0 No response pending
1 Response is pending
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 14-95. PEX_CSB_STAT Register Fields Description
—
—
Figure
14-97, maintains the activity status of the DMA and PIO transactions.
25
9
RDMARP
IBPIORP
24
8
All zeros
All zeros
23
Description
7
—
—
PCI Express Interface Controller
Access: Read only
17
1
WDMARP
OBPIORP
16
0
14-79