MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 883

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Valid combination for protocol select is:
15.5
The SerDes is capable of several different power management states depending on the settings of the
protocol selection and power down signals.
By setting the register field SRDSCR0[24] powers down the entire SerDes and is comparable to the PCI
Express L2 low power link state. The steps for powering down the SerDes are as follows:
Freescale Semiconductor
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1. Apply power to all XCOREVDD, XPADVDD, SDAVDD supplies.
2. Be sure all XCOREVSS, XPADVSS, and SDAVSS supplies are grounded.
3. Assert the SRDSCR0[24] control from the chip logic to whichever SerDes block is not in use. This
4. Tie all unused RXn and RXn serial differential inputs to XCOREVSS.
5. Float all unused TXn and TXn serial differential outputs.
6. If a SerDes block is not being used and has its own receiver and transmitter calibration external
7. Tie SD_REF_CLK and SD_REF_CLK both to XCOREVSS.
SRDSCR4 register
— Configure protocol select, reference clock frequency, and PCI Express ×1 lane (refer to
PCI Express mode (AD_PROTO_SEL/EH_PROTO_SEL[2–0] = 001) is only an ×1 lane. The
reference clock can be either 100 or 125 MHz.
safely parks all the analog circuitry and stops all SerDes-generated clocks.
resistors, then these can be tied to XCOREVDD for the receiver (SD_IMP_CAL_RX) and
XPADVDD for the transmitter (SD_IMP_CAL_TX).
Power Management: Power Down
Figure
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15-6)
The entire SerDes need to be reset in order to activate lane A from
power-down. The SRDSCR4 register is initialized base on
RCWH[TSEC1M] and RCWH[TSEC2M]. The SRDSCR3 register is
not initialized based on RCWH[TSEC1M] and RCWH[TSEC2M]; it
needs to be done explicitly based on the usage scenario. (Refer to
Section 4.3.2.2.4, “eTSEC1
For reset from software, the recommended option is to use
SRDSRSTCTL[RST], and let the hardware control the timing of the
various SERDES resets and power-downs.
Software can poll SRDSRSTCTL[RDONE] to determine when the reset
is complete. For more information, see
Control Register (SRDSRSTCTL).”
If the entire SerDes is powered down, or even if parts of the SerDes is
powered down, all power pads in the SerDes must be powered.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Mode.”)
NOTE
NOTE
Section 15.3.6, “SerDesn Reset
SerDes PHY
15-11