MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 644

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
This area is characterized as an overlay because when the queue is advanced to the next queue element,
the source queue element is merged onto this area. This area serves an execution cache for the transfer.
Table 13-61
13.5.7
The periodic frame span traversal node (FSTN) data structure, shown in
for managing full- and low-speed transactions that span a host-frame boundary. Software must not use an
FSTN in the asynchronous schedule. An FSTN in the asynchronous schedule results in undefined
behavior. Software must not use the FSTN feature with a host controller whose HCIVERSION register
indicates a revision implementation under 0x0096. Note that FSTNs were not defined for EHCI
implementations before Revision 0.96 of the EHCI Specification and their use may yield undefined results.
13-66
DWord
31
5
6
6
6
6
8
9
9
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Offset
0x14
0x18
0x18
0x18
0x18
0x20
0x24
0x24
QH
Periodic Frame Span Traversal Node (FSTN)
describes the host-controller rules for bits in overlay.
Table 13-61. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9)
11–10
11–5
Bits
4–1
7–0
4–0
31
15
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
C-prog-mask
FrameTag
Status[0]
NakCnt
S-bytes
Figure 13-42. Frame Span Traversal Node Structure
Name
Cerr
ioc
dt
Normal Path Link Pointer
Back Path Link Pointer
Nak counter—RW. This field is a counter the host controller decrements
whenever a transaction for the endpoint associated with this queue head results
in a Nak or Nyet response. This counter is reloaded from RL before a transaction
is executed during the first pass of the reclamation list (relative to an
Asynchronous List Restart condition). It is also loaded from RL during an overlay.
Data toggle. The Data toggle control controls whether the host controller
preserves this bit when an overlay operation is performed.
Interrupt on complete. The ioc control bit is always inherited from the source qTD
when the overlay operation is performed.
Error counter. Copied from the qTD during the overlay and written back during
queue advancement.
Ping state (P)/ERR. If the EPS field indicates a high-speed endpoint, then this
field should be preserved during the overlay operation.
Split-transaction complete-split progress. Initialized to zero during any overlay.
This field is used to track the progress of an interrupt split-transaction.
Software must ensure that the S-bytes field in a qTD is zero before activating the
qTD. Keeps track of the number of bytes sent or received during an IN or OUT
split transaction.
Split-transaction frame tag. Initialized to zero during any overlay. This field is used
to track the progress of an interrupt split-transaction.
15
14 13 12 11 10
Description
9
Figure
8
7
6
13-42, is to be used only
5
Freescale Semiconductor
4
00
00
3
2
Typ
Typ
1
T 0x00
T 0x04
0
offset