MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 22

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
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8-32
8-33
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
xxii
Message Shared Interrupt Status Register (MSISR) ............................................................. 8-42
Message Shared Interrupt Index Register (MSIIR) .............................................................. 8-43
DDR Memory Controller Simplified Block Diagram............................................................. 9-2
Chip Select Bounds Registers (CSn_BNDS)........................................................................ 9-11
Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-12
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 9-13
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 9-16
DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-18
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-19
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2) ....................... 9-22
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-23
DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-24
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 9-25
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-27
DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-28
DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 9-28
DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-29
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-29
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-30
Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 9-30
Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-31
Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 9-31
Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-32
Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-32
Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-33
Memory Error Detect Register (ERR_DETECT) ................................................................. 9-33
Memory Error Disable Register (ERR_DISABLE).............................................................. 9-34
Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-35
Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-36
Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-37
Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-37
Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-39
Typical DDR SDRAM Interface Signals .............................................................................. 9-39
Example 64-Mbyte DDR SDRAM Configuration With ECC .............................................. 9-40
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-48
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-48
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-49
DDR SDRAM Clock Distribution Example for ¥8 DDR SDRAMs .................................... 9-49
DDR SDRAM Mode-Set Command Timing ........................................................................ 9-50
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-51
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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