MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 150

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
System Configuration
Table 5-7
5.1.4.3.1
The core may also use a local bus peripheral device to fetch its boot vector. For this purpose, the
LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word
high BMS field.
Table 5-8
5.1.4.4
The LBC local access window n attributes registers (LBLAWAR0–LBLAWAR3) are shown in
Table 5-9
5-8
20–31
0–19
‘
‘
The LBLAWAR0[EN] reset value depends on the reset configuration word high values. See
and LBLAWAR0[SIZE] Reset Value,”
The LBLAWAR0[SIZE] reset value is always 0b010110, meaning an 8-Mbyte local access window. See
“LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”
‘
Bits
Bits
Offset 0x24, 0x2C, 0x34, 0x3C
Reset 0
0
W
R
BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n . The specified
Name
EN
Figure 5-5. LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3)
0
EN
defines the bit fields of LBLAWBAR0–LBLAWBAR3.
defines the reset value of LBLAWBAR0[BASE_ADDR].
defines the bit fields of LBLAWAR0–LBLAWAR3.
1
Name
0
1
—
LBC Local Access Window n Attributes Registers
(LBLAWAR0–LBLAWAR3)
LBLAWBAR0[BASE_ADDR] Reset Value
0 Local bus local access window n is disabled.
1 Local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to
0
identify an address range for this window.
0
base address should be aligned to the window size, as defined by LBLAWARn[SIZE].
Reserved. Write has no effect, read returns 0.
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
RCWHR[BMS]
0
Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value
Table 5-7. LBLAWBAR0–LBLAWBAR3 Bit Settings
0
Table 5-9. LBLAWAR0–LBLAWAR3 Bit Settings
0
1
0
for a detailed description.
0
0
0
0
0
for a detailed description.
—
0
0
Description
0
BASE_ADDR Reset Value
Description
0
0
0
0x00000
0xFF800
0
0
0
Section 5.1.4.4.1, “LBLAWAR0[EN]
0
0
0
Freescale Semiconductor
25 26
0
Section 5.1.4.4.1,
0
Access: Read/Write
0
Figure
SIZE
0
0
0 0
5-5.
31
2