MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 157

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.1.11
In addition to being accessible by the e300 processor, the IMMR memory window is accessible from
external interfaces. This allows external masters on the I/O ports to configure the device.
External masters do not need to know the location of the IMMR memory in the local address map. Rather,
they access this region of the local memory map through a window defined by a register in the interface’s
programming model that is accessible to the external master from its external memory map.
5.2
The following sections describe some general information and configuration options that affect system
behavior and performance.
5.2.1
Table 5-18
Freescale Semiconductor
1
2
Bit #25 depends on the RCW.
Bit #30 depend on RCW.
0x0011C–0x00124
0x00160–0x001FC
Local Memory
Offset (Hex)
0x0010C
0x0012C
0x00100
0x00104
0x00108
0x00110
0x00114
0x00118
0x00128
0x00140
0x00144
0x00148
System Configuration
shows the memory map for the system configuration registers.
Accessing Internal Memory from External Masters
System Configuration Register Memory Map
System general purpose register low (SGPRL)
System general purpose register high (SGPRH)
System part and revision ID register (SPRIDR)
Reserved
System priority configuration register (SPCR)
System I/O configuration register low (SICRL)
System I/O configuration register high (SICRH)
Reserved
DDR control driver register (DDRCDR)
DDR debug status register (DDRDSR)
PCI Express control register 1 (PECR1)
eSDHC control regiser (SDHCCR)
RTC control register (RTCCR)
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 5-18. System Configuration Register Memory Map
System Configuration—Block Base Address 0x0_0000
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
0x0000_0000
0x0014_5000
0x0000_0000
0x0000_0000
0x8101_0010
0x0000_0000
0x7304_0001
0x3300_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
1
2
System Configuration
5.2.2.11/55-28
5.2.2.12/55-29
5.2.2.13/55-31
Section/Page
5.2.2.10/5-27
5.2.2.1/5-16
5.2.2.2/5-16
5.2.2.3/5-17
5.2.2.4/5-17
5.2.2.5/5-19
5.2.2.6/5-22
5.2.2.9/5-26
—
—
—
5-15