MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 374

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
doubleword, a full read-modify-write is performed for a write to SDRAM. If ECC is disabled or both the
access is doubleword aligned with a size that is a multiple of a doubleword, the data masks (MDM[0:4]
for 32-bit bus) can be used to prevent the writing of unwanted data to SDRAM. The DDR memory
controller also uses data masks to prevent all unintended full double words from writing to SDRAM. For
example, if a write transaction is desired with a size of one word (4 bytes), then the second, third, and
fourth beats of data are not written to DRAM (assuming a 32-bit data bus).
Table 9-44
the possible transfer sizes with each of the possible starting double-word offsets. All underlined
double-word offsets are valid for the transaction.
9.5.10
The DDR memory controller supports an open/closed page mode with an allowable open page for each
logical bank of DRAM used. In closed page mode for DDR SDRAMs, the DDR memory controller uses
the SDRAM auto-precharge feature, which allows the controller to indicate that the page must be
automatically closed by the DDR SDRAM after the READ or WRITE access. This is performed using
MA[10] of the address during the COMMAND phase of the access to enable auto-precharge.
Auto-precharge is non-persistent in that it is either enabled or disabled for each individual READ or
WRITE command. It can, however, be enabled or disabled separately for each chip select.
When the DDR memory controller operates in open page mode, it retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following conditions
occurs:
Page mode can dramatically reduce access latencies for page hits. Depending on the memory system
design and timing parameters, using page mode can save two to three clock cycles for subsequent burst
accesses that hit in an active page. Also, better performance can be obtained using more banks, especially
9-56
•
•
•
Refresh interval is met.
The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
There is a logical bank row collision with another transaction that must be issued.
lists the data beat sequencing to and from the DDR SDRAM and the data queues for each of
Page Mode and Logical Bank Retention
1
All underlined and bolded Double-word offsets are valid for the transaction.
2 double words
3 double words
Transfer Size
1 double word
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 9-44. Memory Controller–Data Beat Ordering
Starting Double-Word Offset
0
1
2
3
0
1
2
0
1
Double-Word Sequence
DRAM and Queues
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
1
to/from
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