MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 395

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
19
20
21
22
23
24
BCTLD
Name
CSCT
PGS
CHT
CST
—
Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
Reserved
NAND Flash EEPROM page size, buffer size, and block size.
0 Page size of 512 main area bytes plus 16 spare area bytes (small page devices);
1 Page size of 2048 main area bytes plus 64 spare area bytes (large page devices);
Chip select to command time. Determines how far in advance LCS n is asserted prior to any bus activity
during a NAND Flash access handled by the FCM. This helps meet chip-select setup times for slow
memories.
Command setup time. Determines the delay of LFWE0 assertion relative to the command, address, or data
change when the external memory access is handled by the FCM.
Command hold time. Determines the LFWE0 negation prior to the command, address, or data change
when the external memory access is handled by the FCM.
FCM RAM buffers are 1 Kbyte each; Flash block size of 16 Kbytes.
FCM RAM buffers are 4 Kbytes each; Flash block size of 128 Kbytes.
TRLX
TRLX
TRLX
0
0
1
1
0
0
1
1
0
0
1
1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 10-8. OR n
CSCT
CST
CHT
0
1
0
1
0
1
0
1
0
1
0
1
The chip-select is asserted 1 clock cycle before any command.
The chip-select is asserted 4 clock cycles before any command.
The chip-select is asserted 2 clock cycles before any command.
The chip-select is asserted 8 clock cycles before any command.
The write-enable is asserted coincident with any command.
The write-enable is asserted 0.25 clock cycles after any command, address, or
data.
The write-enable is asserted 0.5 clock cycles after any command, address, or
data.
The write-enable is asserted 1 clock cycle after any command, address, or data.
The write-enable is negated 0.5 clock cycles before any command, address, or
data change.
The write-enable is negated 1 clock cycle before any command, address, or data
change.
The write-enable is negated 1.5 clock cycles before any command, address, or
data change.
The write-enable is negated 2 clock cycles before any command, address, or data
change.
—
FCM Field Descriptions (continued)
Description
Meaning
Meaning
Meaning
Enhanced Local Bus Controller
10-15