MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 399

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.1.4
The UPM machine mode registers (MAMR, MBMR and MCMR), shown in
configuration for the three UPMs.
Table 10-11
Freescale Semiconductor
Offset MAMR: 0x0_5070
Reset
Reset
Bits
2–3
5–7
0
1
4
W
W
R
R
MBMR: 0x0_5074
MCMR: 0x0_5078
—
16
0
UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode.
Name
RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh
RLF
OP
—
—
RFEN
describes UPM mode fields.
UPM Mode Registers (M x MR)
17
1
Reserved
executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no refresh
services can be provided, even if UPMB and/or UPMC have their RFEN bit set.
0 Refresh services are not required
1 Refresh services are required
Command opcode. Determines the command executed by the UPM n when a memory access hits a UPM
assigned bank.
00 Normal operation
01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents of the
10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the contents of
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in the
0 LUPWAIT is active high.
1 LUPWAIT is active low.
Reserved
MDR into the RAM location pointed to by MAD. After the access, MAD is automatically incremented.
the RAM location pointed to by MAD into the MDR. After the access, MAD is automatically incremented.
RAM array. The pattern run starts at the location pointed to by MAD and continues until the LAST bit is
set in the RAM word.
18
2
OP
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
3
WLF
UWPL
Figure 10-7. UPM Mode Registers (M x MR)
4
Table 10-11. M x MR Field Descriptions
21
5
—
22
7
All zeros
All zeros
TLF
Description
8
DS
25
9
10
26
G0CL
Figure
12
Enhanced Local Bus Controller
MAD
10-7, contain the
GPL4
13
Access: Read/Write
14
RLF
10-19
15
31