MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1052

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
16-168
Offset
0–1
10–13
Bits
5
6
7
8
9
Table 16-147. Transmit Data Buffer Descriptor (TxBD) Field Descriptions (continued)
Name
PRE
DEF
HFE
TC
CF
RC
LC
RL
—
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Tx CRC. Written by user. (Valid only while it is set in first BD and TxBD[PAD/CRC] is cleared and
0 End transmission immediately after the last data byte with no hardware generated CRC
1 Transmit the CRC sequence after the last data byte.
Transmit user-defined Ethernet preamble. Written by user. Valid only if set in the first BD of a frame,
and MACCFG2[PreAm TxEN] is set.
0 This frame does not contain Ethernet preamble bytes for transmission.
1 This frame includes a user-defined Ethernet preamble sequence prior to the destination address
Defer indication. The eTSEC updates this bit after transmitting a frame (TxBD[L] is set)
0 This frame was not deferred.
1 This frame did not have a collision before it was sent but it was sent late because of deferring
Reserved
Huge frame enable. Written by user. Valid only if set in the first BD of a frame and MACCFG2[Huge
Frame] is cleared. If MACCFG2[Huge Frame] is set, this bit is ignored.
0 Truncate transmit frame if its length is greater than the MAC’s maximum frame length.
1 Allow large frames to be transmitted without truncation.
Late collision. Written by the eTSEC.
0 No late collision.
1 A collision occurred after 64 bytes are sent. The eTSEC terminates the transmission and
Control Frame. Written by user. Valid only if set in the first BD of a frame.
0 Regular frame; transmission is deferred when eTSEC is in PAUSE.
1 Control frame; transmission starts even if eTSEC is in PAUSE.
Retransmission Limit. Written by the eTSEC.
0 Transmission before maximum retry limit is hit.
1 The transmitter failed (max. retry limit + 1) attempts to successfully send a message due to
Retry Count. Written by the eTSEC.
0 The frame is sent correctly the first time.
x One or more attempts where needed to send the transmit frame. If this field is 15, then 15 or
MACCFG2[PAD/CRC enable] is cleared and MACCFG2[CRC enable] is cleared.) If
MACCFG2[PAD/CRC enable] is set or MACCFG2[CRC enable] is set, this bit is ignored in
ethernet modes.
appended, unless TxBD[PAD/CRC] is set.
in the data buffer.
updates LC.
repeated collisions. The eTSEC terminates the transmission and updates RL.
more retries were needed. The Ethernet controller updates RC after sending the buffer.
Description
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