MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 851
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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The attributes of the outbound windows are controlled by the PEX_OWARn registers and the attributes of
the RC inbound windows are controlled by the PEX_RCIWARn registers, residing in the CSB bridge
address space. The attributes of the EP inbound windows are controlled by both the translation registers,
PEX_EPIWTARn, in the CSB bridge space, and by the PCI Express BAR configuration registers residing
in the PCI Express core address space.
14.6.1.2
Table 14-137
Freescale Semiconductor
Mrd
MRdLk
MWr
IORd
IOWr
CfgRd0
CfgWr0
CfgRd1
CfgWr1
Msg
MsgD
Cpl
Window
Number
PCI Express
Transaction
1
2
3
64-bit address, low portion
64-bit address, high portion
64-bit address, low portion
64-bit address, high portion
64-bit address, low portion
64-bit address, high portion
PCI Express Transactions
lists the PCI Express transactions supported by the device as an initiator and a target.
For outbound transactions, both the PCI Express DMA and CSB Masters
share the same set of windows.
Support as an Initiator
Yes
No
Yes
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes
No
Yes
MPC8378E/MPC8377E
Type
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 14-136. Address Translation Window Combinations
Table 14-137. PCI Express Transactions
Yes
No
Yes
No
No
Yes
Yes
No
No
Yes
No
Yes
MPC8378E/MPC8377E
PEX_RCIWBARH1
PEX_RCIWBARH2
PEX_RCIWBARH3
PEX_RCIWBARL1
PEX_RCIWBARL2
PEX_RCIWBARL3
Support as a Target
BAR Name
NOTE
BAR Address
Memory Read Request
Memory Read Lock
Memory Write Request to memory-mapped
PCI-Express space
I/O Read request
I/O Write Request
Configuration Read Type 0
Configuration Write Type 0
Configuration Read Type 1
Configuration Write Type 1
Message Request
Message Request with data payload
Completion without Data
0x9E7C
0x9E8C
0x9E9C
0x9E78
0x9E88
0x9E98
PEX_RCIWTAR1
PEX_RCIWTAR2
PEX_RCIWTAR3
TAR Name
Definition
PCI Express Interface Controller
TAR Address
0x9E74
0x9E84
0x9E94
14-113
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