MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1103

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-18
18.3.1.12 DMA Status Registers (UDSR1 and UDSR2)
The DMA status registers (UDSRs), shown in
and provide the ability to assist DMA data operations to and from the FIFOs.
Table 18-19
Freescale Semiconductor
Offset: 0x0_4510, 0x0_4610
Bits
Bits
0–5
Reset
0–5
6
7
6
7
W
R
Name
RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
TXRDY
Name
CW
BO
—
—
describes UAFR fields.
describes the fields of the UDSRs.
0
0
Reserved
Baud clock select
0 The baud clock is not gated off.
1 The baud clock is gated off.
Concurrent write enable
0 Disables writing to both UART1 and UART2.
1 Enables concurrent writes to corresponding UART registers. A write to a register in UART1 is also a write
Reserved
Transmitter ready. Reflects the status of the transmitter FIFO or the UTHR. The status depends on the DMA
mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in
1 This bit is set, as shown in
the DMA mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in
1 This bit is set, as shown in
to the corresponding register in UART2 and vice versa.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
0
Figure 18-14. DMA Status Register (UDSR)
Table 18-19. UDSR Field Descriptions
Table 18-18. UAFR Field Descriptions
0
Table
Table
—
Table
Table
Figure
18-20.
18-22.
0
18-21.
18-23.
18-14, return transmitter and receiver FIFO status
Description
Description
0
5
0
TXRDY
Access: User read-only
0
6
RXRDY
1
7
DUART
18-15