MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 823

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.5.5.4
PEX_RDMA_CTRL, shown in
Table 14-103
Freescale Semiconductor
31–11
31–7
Offset 0xA40
Reset
Reset
Bits
Bit
10
6
5
4
3
2
1
0
W
W
R
R
31
15
DSUER
DAFER
DSFER
DSCPL
CHCPL
SNOOP
BRER
Name
PCI Express Read DMA Control Register (PEX_RDMA_CTRL)
Name
defines the bit fields of PEX_RDMA_CTRL.
—
—
Figure 14-105. PCI Express Read DMA Control Register (PEX_RDMA_CTRL)
—
—
Table 14-102. PEX_WDMA_STAT Register Fields Description
Table 14-103. PEX_RDMA_CTRL Register Fields Description
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Reserved
DMA data fetch error. Hardware sets this bit to indicate an error during the data fetch operation.
Bridge error. Hardware sets this bit to indicate that DMA operation cannot complete successfully
because of a CSB bridge error.
Descriptor update error. Hardware sets this bit to indicate an error during descriptor update
operation.
Reserved
Descriptor fetch error. This bit is set by hardware to indicate that a descriptor read from the CSB
has terminated with an error.
Descriptor DMA transfer completed. Hardware sets this bit after completing the transaction for the
descriptor.
DMA chain transfer completed. Hardware sets this bit after completing the transaction in all the
descriptors that are currently programmed. This bit is set when DMA operation is complete and
the DMA controller encounters a NULL descriptor.
Note: When hardware sets this bit it is not guaranteed that the transferred data has fully reached
Reserved
Snoop for write and read transactions to the descriptor. Controls the snooping of the e300 core
on the CSB bus to a transaction initiated by the RDMA. 0 Snoop disabled.
1 Snoop enabled.
its final destination. Software should guarantee this another way. For additional information
see the PEX2 erratum in the errata document of the device.
11
Figure
SNOOP RLXO
10
14-105, controls the RDMA operations.
9
All zeros
8
All zeros
—
Description
Description
—
PCI Express Interface Controller
Access: Read/Write
2
SUS START
1
16
14-85
0