MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 914

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
16.5.3.1.6
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, RPM fields are read-only, having been set after sampling signals at power-on-reset. For
more information, see TSEC mode in
Figure 16-7
Table 16-11
16-30
Offset eTSEC1:0x2_4020; eTSEC2:0x2_5020
Reset
Reset
Bits
30
31
0–16
Bits
17
18
W
W
R
R
—
16
0
PERRDIS
DPEDIS
CLRCNT Clear all statistics counters and carry registers.
Name
AUTOZ
Name
describes the definition for the ECNTRL register.
CLRCNT AUTOZ STEN
describes the fields of the ECNTRL register.
—
Ethernet Control Register (ECNTRL)
17
Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
Receive frame parse error disable.
Reserved
0 Allow MIB counters to continue to increment and keep any overflow indicators.
1 Reset all MIB counters and CAR1 and CAR2.
This bit is self-resetting.
Automatically zero MIB counter values and carry registers.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
18
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-10. EDIS Field Descriptions (continued)
19
Figure 16-7. ECNTRL Register Definition
Table 16-11. ECNTRL Field Descriptions
20
4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
—
All zeros
All zeros
—
24
Description
Description
GMIIM
25
—
26
RPM
27
R100M
28
Freescale Semiconductor
29
Access: Mixed
—
15
31