MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 997

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5.3.10.3 Timer Event Mask Register (TMR_TEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 16-111 describes
the definition for the TMR_TEMASK register.
Table 16-112
16.5.3.10.4 Timer PTP Packet Event Register (TMR_PEVENT)
The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position. Figure 16-107 describes the definition for the
TMR_PEVENT register.
Freescale Semiconductor
Offset eTSEC1:0x2_4E08
Reset
Reset
16–23
27–31
8–13
Bits
0–5
14
15
24
25
26
6
7
W
W
R
R
16
0
ALM2EN
ALM1EN
ETS2EN
ETS1EN
PP1EN
PP2EN
PP3EN
Name
describes the fields of the TMR_TEMASK register fields for the timer.
—
—
—
—
—
Reserved
External trigger 2 timestamp sample event enable
External trigger 1 timestamp sample event enable
Reserved
Timer ALM1 event enable
Timer ALM2 event enable
Reserved
Periodic pulse event 1 enable
Periodic pulse event 2 enable
Periodic pulse event 3 enable
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-112. TMR_TEMASK Register Field Descriptions
—
Table 16-111. TMR_TEMASK Register Definition
5
ETS2EN ETS1EN
6
23
7
All zeros
All zeros
PP1EN PP2EN PP3EN
24
8
Description
25
—
Enhanced Three-Speed Ethernet Controllers
26
27
13
Access: Read/Write
ALM2EN ALM1EN
—
14
16-113
15
31