MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 682

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.6.12.2.9 Rebalancing the Periodic Schedule
System software must occasionally adjust a periodic queue head's S-mask and C-mask fields during
operation. This need occurs when adjustments to the periodic schedule create a new bandwidth budget and
one or more queue head's are assigned new execution footprints (that is, new S-mask and C-mask values).
It is imperative that system software must not update these masks to new values in the midst of a split
transaction. In order to avoid any race conditions with the update, the host controller provides a simple
assist to system software. System software sets the Inactivate-on-next-Transaction (I) bit to signal the host
controller that it intends to update the S-mask and C-mask on this queue head. System software then waits
for the host controller to observe the I-bit is set and transitions the Active bit to a zero. The rules for how
and when the host controller clears the Active bit are:
System software must save transfer state before setting the I-bit. This is required so that it can correctly
determine what transfer progress (if any) occurred after the I-bit was set and the host controller executed
it's final bus-transaction and cleared the Active bit.
After system software has updated the S-mask and C-mask, it must then reactivate the queue head. Since
the Active bit and the I-bit cannot be updated with the same write, system software needs to use the
following algorithm to coherently re-activate a queue head that has been stopped using the I-bit.
Setting the Halted bit inhibits the host controller from attempting to advance the queue between the time
the I-bit is cleared and the Active bit is set.
13.6.12.3 Split Transaction Isochronous
Full-speed isochronous transfers are managed using the split-transaction protocol through a USB 2.0
transaction translator in a USB 2.0 hub. The host controller utilizes siTD data structure to support the
special requirements of isochronous split-transactions. This data structure uses the scheduling model of
isochronous TDs (see
model of iTDs) with the contiguous data feature provided by queue heads. This simple arrangement allows
13-104
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•
•
1. Set the Halted bit, then
2. Clear the I-bit, then
3. Set the Active bit and clear the Halted bit in the same write.
Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of
FRINDEX[2–0] is not 6, or currently in Do Complete Split and the current value of
(FRINDEX[2–0]) is not 7, FrameTag is set to FRINDEX[7–3]. This accommodates all other cases
in
If the Active bit is cleared, no action is taken. The host controller does not attempt to advance the
queue when the I-bit is set.
If the Active bit is set and the SplitXState is DoStart (regardless of the value of S-mask), the host
controller simply clears the Active bit. The host controller is not required to write the transfer state
back to the current qTD. Note that if the S-mask indicates that a start-split is scheduled for the
current microframe, the host controller must not issue the start-split bus transaction; it must clear
the Active bit.
Figure
13-53.
Section 13.6.8, “Managing Isochronous Transfers Using iTDs,”
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor
for the operational