MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 117

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.1.2
The example described in
input signal (CFG_RESET_SOURCE). The reset sequence duration is measured from the negation of
PORESET to the negation of HRESET. Note that the duration mentioned in
not represent cases in which the process of loading the reset configuration word had to be retried due to
errors.
4.3.2
The reset configuration words control the clock ratios and other basic device functions, such as, boot
location, eTSEC mode, and endian mode. The reset configuration words are loaded from NOR Flash,
NAND Flash, or the I
Section 4.3.1, “Reset Configuration Signals,”
Although the configuration reset words are loaded during hard reset flows, the clocks and PLL modes are
reset only when PORESET is asserted during a power-on reset flow. See
The values of fields in the reset configuration words registers (RCWLR and RCWHR) reflect only their
state during the reset flow. Some of these parameters and modes can be modified by changing their values
in the memory-mapped registers of other units, which does not affect RCWLR and RCWHR.
The reset configuration settings are accessible to software through the following read-only
memory-mapped registers:
See
Freescale Semiconductor
•
•
•
•
Section 4.5, “Memory Map/Register Definitions.”
Configuration
Reset configuration word low register (RCWLR)
Reset configuration word high register (RCWHR)
Reset status register (RSR)
System PLL mode register (SPMR)
I
2
C EEPROM
Words
Reset Configuration Words
Yes
No
Selecting Reset Configuration Input Signals
SYS_CLK_IN
2
Frequency
C interfaces or from hard-coded values during the power-on or hard reset flows. See
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
33 MHz
33 MHz
Table 4-6
Table 4-6. Selecting Reset Configuration Input Signals
0000
(RCW loaded from NOR Flash)
0100 (I
shows how the user should pull down or pull up the reset configuration
CFG_RESET_SOURCE[0:3]
2
C EEPROM)
for information on the reset configuration word source.
SYS_CLK_IN Cycles
Reset Sequence
Duration in
Section 4.2.1.2, “Reset Actions.”
106534
15210
Table 4-6
Reset, Clocking, and Initialization
is typical, and does
Duration
456
196
μ
μ
s
s
4-9