MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 680

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13-102
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See above description for testing for Last. The complete-split transaction received a NYET
response from the transaction translator. Do not update any transfer state (except for C-prog-mask
and FrameTag) and stay in this state. The host controller must not adjust Cerr on this response.
Transaction Error (XactErr). Timeout, data CRC failure, etc.
The Cerr field is decremented and the XactErr bit in the Status field is set. The complete split
transaction is immediately retried (if Cerr is non-zero).If there is not enough time in the microframe
to complete the retry and the endpoint is an IN, or Cerr is decremented to a zero from a one, the
queue is halted. If there is not enough time in the microframe to complete the retry and the endpoint
is an OUT and Cerr is not zero, then this state is exited (that is, return to Do Start Split). This results
in a retry of the entire OUT split transaction, at the next poll period. Refer to Chapter 11 Hubs
(specifically the section on full- and low-speed interrupts) in the USB Specification Revision 2.0
for detailed requirements on why these errors must be immediately retried.
ACK
This can only occur if the target endpoint is an OUT. The target endpoint ACK'd the data and this
response is a propagation of the endpoint ACK up to the host controller. The host controller must
advance the state of the transfer. The Current Offset field is incremented by Maximum Packet
Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the
same amount. And the data toggle bit (dt) is toggled. The host controller will then exit this state for
this queue head. The host controller must reload Cerr with maximum value on this response.
Advancing the transfer state may cause other process events such as retirement of the qTD and
advancement of the queue.
MDATA
This response will only occur for an IN endpoint. The transaction translator responded with zero
or more bytes of data and an MDATA PID. The incremental number of bytes received is
accumulated in QH[S-bytes]. The host controller must not adjust Cerr on this response.
DATA0/1
This response may only occur for an IN endpoint. The number of bytes received is added to the
accumulated byte count in QH[S-bytes]. The state of the transfer is advanced by the result and the
host controller exits this state for this queue head.
Advancing the transfer state may cause other processing events such as retirement of the qTD and
advancement of the queue.
If the data sequence PID does not match the expected, the entirety of the data received in this split
transaction is ignored, the transfer state is not advanced and this state is exited.
NAK
The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not
advanced, and this state is exited. The host controller must reload Cerr with maximum value on
this response.
ERR
There was an error during the full- or low-speed transaction. The ERR status bit is set, Cerr is
decremented, the state of the transfer is not advanced, and this state is exited.
STALL
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor