MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 59

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor,
San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture
in general:
Related Documentation
Freescale documentation is available from the sources listed on the back cover of this manual:
Freescale Semiconductor
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Chapter 18, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
Chapter 19, “Serial Peripheral Interface,”
that allows the exchange of data between the MPC8308 and MPC83xx family of devices. The SPI
can also be used to communicate with peripheral devices such as EEPROMs, real-time clocks, A/D
converters, and ISDN devices.
Chapter 20, “JTAG/Testing Support,”
MPC8308 to facilitate boundary-scan testing. The JTAG interface complies to the IEEE 1149.1™
boundary-scan specification.
Chapter 21, “General Purpose I/O (GPIO),”
the MPC8308, including a definition of the external signals and functions they serve. Additionally,
interrupt capabilities, pin description, and register settings are described.
Appendix A, “Complete List of Configuration, Control, and Status Registers,”
used with the MPC8308.
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David
A. Patterson.
Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David
A. Patterson and John L. Hennessy.
e300 Core Reference Manual—This book provides a more detailed description of the e300 core.
MPC8308 PowerQUICC II Pro Processor Device Errata—This document details all known
silicon errata for the Freescale IPs in the MPC8308.
MPC8308 PowerQUICC II Pro Processor Hardware Specification—This document provides an
overview of the MPC8308 features, its hardware specifications, including a block diagram
showing the major functional components. Hardware specifications provide specific data
regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other
design considerations.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
describes the (dual) universal asynchronous receiver/transmitters
describes the joint test action group (JTAG) interface of the
describes the MPC8308 serial peripheral interface (SPI)
describes the general purpose I/O (GPIO) module in
lists all the registers
lix