MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 691

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

These fields are then written back to the memory based siTD. The S-mask is fixed for the life of the current
budget. As mentioned above, TP and T-count are set specifically in each siTD to reflect the data to be sent
from this siTD. Therefore, regardless of the value of S-mask, the actual number of start-split transactions
depends on T-count (or equivalently, Total Bytes to Transfer). The host controller must clear the Active bit
when it detects that all of the schedule data has been sent to the bus. The preferred method is to detect when
T-Count decrements to zero as a result of a start-split bus transaction. Equivalently, the host controller can
detect when Total Bytes to Transfer decrements to zero. Either implementation must ensure that if the
initial condition is Total Bytes to Transfer is equal to zero and T-count is equal to a one, the host controller
issues a single start-split, with a zero-length data payload. Software must ensure that TP, T-count and Total
Bytes to Transfer are set to deliver the appropriate number of bus transactions from each siTD. An
inconsistent combination yields undefined behavior.
If the host experiences hold-offs that cause the host controller to skip start-split transactions for an OUT
transfer, the state of the transfer does not progress appropriately. The transaction translator observes
protocol violations in the arrival of the start-splits for the OUT endpoint (that is, the transaction position
annotation is incorrect as received by the transaction translator).
Example scenarios are described in
Example.”
The host controller can optionally track the progress of an OUT split transaction by setting appropriate bits
in the siTD[C-prog-mask] as it executes each scheduled start-split. The checkPreviousBit() algorithm
defined in
executing each start-split to determine whether start-splits were skipped. The host controller can use this
mechanism to detect missed microframes. It can then clear the siTD's Active bit and stop execution of this
siTD. This saves on both memory and high-speed bus bandwidth.
13.6.12.3.5 Periodic Isochronous—Do Complete Split
This state is only used by a split-transaction isochronous IN endpoint. This state is entered unconditionally
from the Do Start State after a start-split transaction is executed for an IN endpoint. Each time the host
controller visits an siTD in this state, it conducts a number of tests to determine whether it should execute
a complete-split transaction. The sequence in which they are applied depends on which microframe the
host controller is currently executing, which means that the tests might not be applied until after the siTD
referenced from the back pointer has been fetched. The individual tests are as follows.
Freescale Semiconductor
•
•
•
The siTD[TP] and siTD[T-count] fields are updated appropriately as defined in
Test A
cMicroFrameBit is bit-wise ANDed with the siTD[C-mask] field. A non-zero result indicates that
software scheduled a complete-split for this endpoint, during this microframe. This test is always
applied to a newly fetched siTD that is in this state.
Test B
The siTD[C-prog-mask] bit vector is checked to determine whether the previous complete splits
have been executed. An example algorithm is given below (this is slightly different than the
algorithm used in
which this test is applied depends on the current value of FRINDEX[2–0]. If FRINDEX[2–0] is 0
or 1, it is not applied until the back pointer has been used. Otherwise it is applied immediately.
Section 13.6.12.3.5, “Periodic Isochronous—Do Complete Split,”
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Section 13.6.12.2.7, “Periodic
Section 13.6.12.3.7, “Split Transaction for Isochronous—Processing
Interrupt—Do-Complete-Split”). The sequence in
can be used prior to
Universal Serial Bus Interface
Table
13-70.
13-113