MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 754

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
the PCI Express device control register described in
Register,”
Advanced Error Reporting Capability ID Register,”
Identification Register.”
Table 14-6
14-16
Offset 0x004
Reset
15–9
Bits
5–3
8
7
6
2
1
0
W
R
15
Bus master Enables/disables this PCI Express device to behave as a PCI Express bus master.
Parity error
I/O space I/O space. This bit is hardwired to 0.
response
Memory
Name
SERR
space
and the advance error reporting capability structure described in
describes the bits of the command register.
—
—
—
Reserved
Controls the reporting of fatal and non-fatal errors detected by the device to the root complex.
0 Disables reporting
1 Enables reporting
Reserved
Controls whether this PCI Express controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI Express status register to be set. However, note that
Reserved
0 Disables the ability to generate PCI Express accesses.
1 Enables this PCI Express controller to behave as a bus master.
Clearing this bit prevent the device from issuing any memory or I/O transactions. Because MSI interrupts
are effectively memory writes, clearing this bit also disables the ability of the device to issue MSI interrupts.
Controls whether this PCI Express device (as a target) responds to memory accesses.
0 Device does not respond to PCI Express memory space accesses.
1 Device responds to PCI Express memory space accesses.
Clearing this bit prevents the device from accepting any memory transaction. It does not affect outbound
memory transactions.
errors are reported based on the values set in the PCI Express error enable and detection registers.
—
Table 14-6. PCI Express Command Register Fields Description
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 14-5. PCI Express Command Register
9
SERR
8
— Parity error
7
through
All zeros
Section 14.4.4.10, “PCI Express Device Control
response
Description
6
Section 14.4.5.11, “PCI Express Error Source
5
—
3
Section 14.4.5.1, “PCI Express
Bus master
2
Freescale Semiconductor
Memory
space
1
Access: Mixed
I/O space
0