MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 813

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The fields of the PEX_PME_TO_ACK_TOR are described in
14.4.8.2
The PME_To_Ack Status Register (PEX_PME_TO_ACK_SR) shown in
power manager software to decide whether it is safe to switch off power to downstream devices, after
PME_Turn_Off message has been broadcast by the root port.
The fields of the PEX_PME_TO_ACK_SR are described in
Freescale Semiconductor
Offset 0x594
Reset
31–22
21–0
31–3
Bits
Bits
2
1
0
W
R
31
PME_TO_ACK_
PTACKMR
TIMEOUT
PTACKTO
L2L3RDY
Name
Name
PME_To_Ack Status Register (RC Mode Only)
—
—
Figure 14-93. PME_To_Ack Status Register (PEX_PME_TO_ACK_SR)
Reserved
After the RC broadcasts a PME_Turn_Off message, the power management module waits for the
duration of the PME_To_Ack timeout interval to receive a PME_To_Ack message from the
downstream device. If the Ack message is not received within this interval, the power manager
indicates that it is safe to switch off power because a timeout has occurred.
The value is calculated as:
The recommended timeout duration is 1 msec to 10 msec to make sure that the downstream
devices get enough time to prepare for power-off condition.
Reserved
PME_To_Ack timeout occurred. This bit is set by the hardware when PME_To_Ack message is not
received by the Root Port from downstream device within the timeout duration indicated by
PME_To_ACk_timeout register. When this bit is set, it is safe for the Power manager to switch off
the power of the downstream device. Once set, this bit will remain set, till software clears it by writing
1’b1 to this bit.
Entered L2/L3 ready state. This bit is set by hardware when the current power management
state is L2/L3 Ready. 100nsec after this bit is set, it is safe for the Power manager to switch off the
power of the downstream device. Once set, this bit will remain set, till software clears it by writing
1’b1 to this bit.
PME_To_Ack message received. This bit is set by hardware when PME_To_Ack message is
received by the Root Port from the downstream device. When this bit is set, it is safe for the Power
manager to switch off the power of the downstream device. Once set, this bit will remain set, till
software clears it by writing 1’b1 to this bit.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 14-90. PEX_PME_TO_ACK_TOR Fields Description
Table 14-91. PEX_PME_TO_ACK_SR Fields Description
Time (in µsec) × PCI Express controller core clock frequency (in MHz)
—
All zeros
Description
Description
Table
Table
14-91.
3
14-90.
PTACKTO
Figure
w1c
2
PCI Express Interface Controller
14-93, can be used by the
L2L3RDY
w1c
1
Access: w1c
PTACKMR
w1c
0
14-75