MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 300

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
8.5.17
SERCR, shown in
MCP_OUT
Table 8-26
8.5.18
SEPCR, shown in
determines whether the corresponding IRQn signal is treated as active low or active high signal. The active
low signals will assert an interrupt request upon either a high-to-low change or assertion (low state) on the
pin. The active high signals assert an interrupt request upon either a low-to-high change or assertion (high
state) on the pin. See
for more details.
8-26
Offset 0x48
Reset
0–30
Bits
31
W
R
0
defines the bit fields of SERCR.
System Error Control Register (SERCR)
System External interrupt Polarity Control Register (SEPCR)
MCPR
Name
—
Note that the IRQn signals are overbarred although the SEPCR could be
programmed to accept active high signals. The overbar should be ignored in
this case.
Figure
Figure
Section 8.5.14, “System External Interrupt Control Register (SECNR),” on page 8-23
Write ignored, read = 0
MCP route. Route MCP request to MCP_OUT.
0 MCP is not available at MCP_OUT
1 MCP routed to MCP_OUT.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
8-21, defines the polarity for each one of the external IRQn interrupt signals and
8-20, defines the control bits that route MCP requests in core disable mode to
Figure 8-20. System Error Control Register (SERCR)
Table 8-26. SERCR Field Descriptions
NOTE
—
All zeros
Description
Freescale Semiconductor
Access: Read/write
30
MCPR
31