MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 201

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The GTCFR2 register is shown in
Freescale Semiconductor
Offset
Bits
2
3
4
5
6
7
Reset
W
R
0x04
Name
STP2
RST2
STP1
RST1
GM2
GM1
PCAS
0
Stop timer 2
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 2, except the
Reset timer 2
0 Reset the timer 2, including GTMDR2, GTRFR2, GTCNR2, GTCPR2, and GTEVR2 (a software reset is
1 Enable the corresponding timer if the STP2 bit is cleared.
Gate mode for TGATE2
0 Restart gate mode. The TGATE2 pin is used to enable/disable count. A low level of TGATE2 enables and
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart the
Gate mode for TGATE1
0 Restart gate mode. The TGATE1 is used to enable/disable count. A low level of TGATE1 enables and a
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart the
Note: In backward-compatible mode (GTCFR1[BCM] = 0) this bit is ignored. GTCFR1[GM2] bit controls the
Stop timer 1
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 1, except the
Reset timer 1
0 Reset the timer 1, including GTMDR1, GTRFR1, GTCNR1, GTCPR1, and GTEVR1 (a software reset is
1 Enable the corresponding timer if the STP1 bit is cleared.
Register Interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
a falling edge of TGATE2 restarts the count (reset the dynamic counter’s count value to 0) and a high
level of TGATE2 disables the count.
appropriate count value in GTCNR2[CNV2].
falling edge of TGATE1 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE1 disables the count.
appropriate count value in GTCNR1[CNV1].
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
Figure 5-44. Global Timers Configuration Register 2 (GTCFR2)
gate mode for timers 1 and 2.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
SCAS
1
Table 5-56. GTCFR1 Bit Settings (continued)
Figure
STP4
2
5-44.
RST4
3
All zeros
Description
GM4
4
GM3
5
STP3
6
System Configuration
Access: Read/Write
RST3
7
5-59