MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 816

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 14-93
14.5.2.2
PEX_DMA_DSTMR, shown in
before reading the next descriptor once it encounters a descriptor that is not ready. The timer should be
programmed to allow sufficient number of clocks before the DMA tries to fetch the descriptors again.
Table 14-94
14-78
Offset 0x814
Reset
31–10
31–0
Bits
Bits
9–8
7–4
3
2
1
0
W
R
31
WDMAE
OBPIOE
RDMAE
IBPIOE
defines the bit fields of PEX_CSB_CTRL.
Name
DSAD
defines the bit field for PEX_DMA_DSTMR.
PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR)
Figure 14-96. PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR)
—
—
Name
DSRT
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Reserved
Depth of descriptors array. Indicates the number of descriptors that should be placed at a
contiguous addresses block. The PCI Express controller DMA uses this information to fetch each
block of descriptors by a burst transaction. The implicit address of the next descriptor is the next
memory location. The last descriptor in the contiguous block contains the explicit address pointer
of the next set of descriptors. See
Note that for most usages this field should be programmed to 00.
00 1—Single fetch descriptor chain mode. Each descriptor explicitly contains the address of the
01 2—Burst fetch descriptor chain mode. The PCI Express controller will fetch two contiguous
10 4—Burst fetch descriptor chain mode. The PCI Express controller will fetch four contiguous
11 Reserved
Reserved
Read DMA enable. Must be set to enable the read DMA operation.
Write DMA enable. Must be set to enable the write DMA operation.
Inbound PIO enable. Must be set to enable the PCI Express Inbound PIO operation.
Outbound PIO enable.Must be set to enable the PCI Express outbound PIO operation.
Table 14-93. PEX_CSB_CTRL Register Fields Description
next descriptor.
descriptors in a burst.
descriptors in a burst.
Table 14-94. PEX_DMA_DSTMR Fields Description
Descriptor ready timer. Represents the number of CSB bridge clocks that the DMA engine
should wait before checking whether the next descriptor is ready when it encounters invalid
descriptor.
Figure
14-96, contains the timer value the DMA engine should wait for
Section 14.8.4, “Descriptor-Based DMA,”
All zeros
DSRT
Description
Description
Freescale Semiconductor
for detailed description.
Access: Read/Write
0