MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 127

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.3.2.3
The I
be the first 3 bytes programmed into the EEPROM. It should have a value of 0xAA_55AA. The I
module checks to ensure that this preamble is correctly detected before proceeding further. Following the
preamble, there should be the two reset configuration words, programmed according to a particular format,
as shown in
The first 3 bytes hold the attributes and address offset. The addresses of the two reset configuration words
must be programmed to the offset of the reset configuration word low register (RCWLR) and reset
configuration word high register (RCWHR) respectively (see
Low Register (RCWLR),”
The attributes should be programmed as follows: alternate configuration space (ACS) should be cleared
(0b0), byte enables should be all ones, and continue (CONT) should be set.
After the first 3 bytes, 4 bytes of data should hold the desired value of the reset configuration word. The
boot sequencer assumes that a big-endian address is stored in the EEPROM.
IMMRBAR value is prepended to the EEPROM address to generate the complete memory-mapped
register’s address.
When the I
as any registers following the first two reset configuration words.
Figure 4-6
configuration words and additional initialization data. In this example, it is assumed that the EEPROM
Freescale Semiconductor
2
C module expects that a particular data format be used for data in the EEPROM. A preamble should
2
shows an example of the CRC and EEPROM contents, including the preamble, reset
Figure 4-5. EEPROM Data Format for Reset Configuration Words Preload Command
C operates in reset configuration mode, the cyclic redundancy check (CRC) is ignored, as well
Figure
EEPROM Data Format in Reset Configuration Mode
4-5.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
ACS
ACS
(0)
(0)
0
and
Section 4.5.1.2, “Reset Configuration Word High Register
1
Reset configuration word high [16–23]
Reset configuration word high [24–31]
Reset configuration word low [16–23]
Reset configuration word low [24–31]
Reset configuration word high [8–15]
Reset configuration word low [8–15]
Reset configuration word high [0–7]
Reset configuration word low [0–7]
BYTE_EN
BYTE_EN
(1111)
(1111)
RCWHR ADDR[14–21]
RCWHR ADDR[22–29]
RCWLR ADDR[14:21]
RCWLR ADDR[22:29]
4
CONT
CONT
Section 4.5.1.1, “Reset Configuration Word
(1)
(1)
5
ADDR[12–13]
ADDR[12–13]
6
RCWHR
RCWLR
7
Reset, Clocking, and Initialization
(RCWHR)”).
2
C
4-19