MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 133

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4.2
The clock signal (USB_CLK_IN) is given from an external source. For more details refer to
“Universal Serial Bus Interface.”
4.4.3
When running in RGMII mode, the reference clocks are TSECn_GTX_CLK125 and TSECn_RX_CLK
input on the eTSEC1 and eTSEC2 interface. This can either be a 2.5- or 3.3-V signal.
When running in the MII mode, the reference clocks are TSECn_TX_CLK and TSECn_RX_CLK input
on the eTSEC1 and eTSEC2 interface. This can be either a 2.5- or 3.3-V signal.
For more information, see
4.5
This section presents memory maps and register descriptions for both reset and clocking.
4.5.1
The reset configuration and status registers are shown in
4.5.1.1
The reset configuration word low register (RCWLR) is shown in
Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR).”
Freescale Semiconductor
0x0_0908–
0x0_0928–
0x0_090C
0x0_091C
0x0_09FC
0x0_0900
0x0_0904
0x0_0910
0x0_0914
0x0_0918
0x0_0920
0x0_0924
Address
Memory Map/Register Definitions
USB Clocking
Ethernet Clocking
Reset Configuration Register Descriptions
Reset Configuration Word Low Register (RCWLR)
Reset configuration word low register (RCWLR)
Reset configuration word high register (RCWHR)
Reserved, should be cleared
Reset status register (RSR)
Reset mode register (RMR)
Reset protection register (RPR)
Reset control register (RCR)
Reset control enable register (RCER)
Reserved.
Reserved, should be cleared
Table 4-24. Reset Configuration and Status Registers Memory Map
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Chapter 16, “Enhanced Three-Speed Ethernet Controllers.”
Reset Configuration—Block Base Address 0x0_0900
Register
Table
4-24.
Access
R/W
R/W
R/W
R/W
R/W
Figure 4-3
—
—
—
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
and described in
Reset, Clocking, and Initialization
Reset
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Section/Page
4.5.1.1/4-25
4.5.1.2/4-26
4.5.1.3/4-26
4.5.1.4/4-27
4.5.1.5/4-28
4.5.1.6/4-28
4.5.1.7/4-29
Chapter 13,
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4-25