MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 642
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Universal Serial Bus Interface
13-64
13–12
31–30
29–23
22–16
11–8
Bits
Bits
6–0
14
7
Device Address Selects the specific device serving as the data source or sink.
Port Number
Hub Addr
Name
EndPt
Name
EPS
Mult
dtc
I
Table 13-58. Endpoint Characteristics: Queue Head DWord 1 (continued)
Data toggle control (DTC). Specifies where the host controller should get the initial data toggle on
an overlay transition.
0 Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head.
1 Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue
Endpoint speed. This is the speed of the associated endpoint.
00 Full-speed (12 Mbps)
01 Low-speed (1.5 Mbps)
10 High-speed (480 Mbps)
11 Reserved, should be cleared This field must not be modified by the host controller.
Endpoint number. Selects the particular endpoint number on the device serving as the data source
or sink.
Inactivate on next transaction. This bit is used by system software to request that the host controller
set the Active bit to zero. This field is only valid when the queue head is in the periodic schedule and
the EPS field indicates a full- or low-speed endpoint. Setting this bit when the queue head is in the
asynchronous schedule or the EPS field indicates a high-speed device yields undefined results.
High-bandwidth pipe multiplier. This field is a multiplier used to key the host controller as the number
of successive packets the host controller may submit to the endpoint in the current execution. The
host controller makes the simplifying assumption that software properly initializes this field
(regardless of location of queue head in the schedules or other run time parameters).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per microframe
10 Two transactions to be issued for this endpoint per microframe
11 Three transactions to be issued for this endpoint per microframe
This field is ignored by the host controller unless the EPS field indicates a full- or low-speed device.
The value is the port number identifier on the USB 2.0 hub (for hub at device address Hub Addr
below), below which the full- or low-speed device associated with this endpoint is attached. This
information is used in the split-transaction protocol.
This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device.
The value is the USB device address of the USB 2.0 hub below which the full- or low-speed device
associated with this endpoint is attached. This field is used in the split-transaction protocol.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 13-59. Endpoint Capabilities: Queue Head DWord 2
head from the DT bit in the qTD.
Description
Description
Freescale Semiconductor
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