MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 742

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
14.1.3
The following is a list of PCI Express controller features:
14.1.4
This section describes how some parameters that affect the PCI Express controller operating modes are
determined by dedicated memory mapped registers.
14.1.4.1
The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) device. The
PCI Express control registers 1 and 2 determine the RC/EP mode; see
Control Registers
14.1.4.2
The link width of the PCI Express controller is ×1.
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Designed to be compatible with the PCI Express Base Specification, Version 1.0a
Root complex (RC) and endpoint (EP) configurations
32- and 64-bit address support
PCI Express link of ×1 lane
Access to all PCI Express memory
Access to I/O address spaces as requestor only in RC mode
Posting of processor-to-PCI Express and PCI Express-to-memory writes
Strong and relaxed transaction ordering rules
PCI Express configuration registers
Baseline and advanced error reporting
One virtual channel (VC0)
128-byte maximum payload size (Max_Payload_Size) for memory read and write operations
Four inbound general-purpose translation windows
Four outbound translation windows
Up to four outstanding PCI Express transactions from each controller (posted or non-posted)
Credit-based flow control management
PCI Express messages and interrupts
Maximum 32-byte payload transactions from the CSB
Interrupt generation from messages or upon detection of errors
Read and Write DMA engines
Support polarity inversion
Features
Modes of Operation
Root Complex/Endpoint Modes
Link Width
(PECR1).”
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Section 5.2.2.11, “PCI Express
Freescale Semiconductor