MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1025

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.6.3.2
TOE functions for transmit are defined by the contents of the Tx FCB.
definition for the Tx FCB.
The user instructs the Tx packet to be timestamped via setting bit 15 in the TxFCB to mark a PTP packet.
TxFCB[VLCTL] can be translated as the Tx PTP packet identification number. BD[TOE] has to be set to
enable transmit PTP packet time stamping. TxFCB[PTP] bit takes precedence over TxFCB[VLN] bit. It
disables per packet VLAN tag insertion. On a PTP packet, VLAN tag can be inserted from the DFVLAN
register. A proposed TxFCB update for the PTP packet is shown in
The contents of the Tx FCB are defined in
Freescale Semiconductor
Bytes
0–1
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Bits
0
1
2
3
4
Transmit Path Off-Load and Tx PTP Packet Parsing
VLN
0
Name
TUP
UDP
VLN
IP6
IP
IP
1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
IP6
Table 16-136. Tx Frame Control Block Description
2
VLAN control word valid. This bit is ignored when the PTP bit is set. VLAN tag is read from
the DFVLAN register if PTP=1.
0 Ignore VLCTL field.
1 If VLAN tag insertion is enabled for eTSEC, use the VLCTL field as the VLAN control
Layer 3 header is an IP header.
0 Ignore layer 3 and higher headers.
1 Assume that the layer 3 header is an IPv4 or IPv6 header, and take L3OS field as valid.
IP header is IP version 6. Valid only if IP = 1.
0 IP header version is 4.
1 IP header version is 6.
Layer 4 header is a TCP or UDP header.
0 Do not process any layer 4 header.
1 Assume that the layer 4 header is either TCP or UDP (see UDP bit), and offload
UDP protocol at layer 4.
0 Layer 4 protocol is either TCP (if TUP = 1) or undefined.
1 Layer 4 protocol is UDP if TUP = 1.
Figure 16-123. Transmit Frame Control Block
word.
checksumming on the basis that the IP header has no extension headers.
TUP UDP CIP CTU NPH
3
L4OS
4
Table
5
16-136.
6
7
VLCTL
PHCS
8
Description
9
Figure
Enhanced Three-Speed Ethernet Controllers
10
Figure 16-123
16-128.
11
L3OS
12
describes the
13
14
PTP
15
16-141