MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1055

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.7
This section discusses the following:
Freescale Semiconductor
Offset Bits
0–1
2–3
4–7
•
•
0–15
0–31 RX Data
Section 16.7.1, “Interface Mode Configuration”
Section 16.7.2, “MAC: Half-Duplex Collision on FCS of Short Frame”
10
11
12
13
14
15
8
9
Initialization/Application Information
Length
Pointer
Name
Buffer
Data
MC
NO
CR
BC
LG
SH
OV
TR
Table 16-148. Receive Buffer Descriptor Field Descriptions (continued)
Broadcast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is broadcast
(FF-FF-FF-FF-FF-FF).
Multicast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is multicast and not BC.
Rx frame length violation, written by the eTSEC (only valid if L is set).
A frame length greater than or equal to the maximum frame length was recognized; in this case LG is
set regardless of the setting of MACCFG2[Huge Frame]. If MACCFG2[Huge Frame] is cleared, the
frame is truncated to the value programmed in the maximum frame length register. This bit is valid only
if the L bit is set.
Rx non-octet aligned frame, written by the eTSEC (only valid if L is set).
A frame that contained a number of bits not divisible by eight was received.
Short frame, written by the eTSEC (only valid if L is set). A frame length less than the minimum
64 bytes that is defined for Ethernet. was recognized, provided RCTRL[RSF] is set.
Rx CRC error, written by the eTSEC (only valid if L is set).
This frame contains a CRC error and is an integral number of octets in length. This bit is also set if a
receive code group error is detected.
Overrun, written by the eTSEC (only valid if L is set).
A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG,
NO, CR and TR lose their normal meaning and are zero.
Truncation, written by the eTSEC (only valid if L is set).
Set if the receive frame is truncated. This can happen if a frame length greater than the maximum
frame length is received and MACCFG2[Huge Frame] is cleared. If this bit is set, the frame must be
discarded and the other error bits must be ignored as they may be incorrect.
Data length, written by the eTSEC.
Data length is the number of octets written by the eTSEC into this BD’s data buffer if L is cleared (the
value is equal to MRBLR), or, if L is set, the length of the frame including CRC, FCB (if
RCTRL[PRSDEP > 00), preamble (if MACCFG2[PreAmRxEn] = 1), timestamp (if RCTRL[TS]=1) and
any padding (RCTRL[PAL]).
Receive buffer pointer, written by the user.
The receive buffer pointer, which always points to the first location of the associated data buffer, must
be 8-byte aligned. For best performance, use 64-byte aligned receive buffer pointer addresses. The
buffer must reside in memory external to the eTSEC.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Description
Enhanced Three-Speed Ethernet Controllers
16-171