MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 507

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11-16
set, the data transfer can be considered complete.
The relation between command CRC error and command timeout error is shown in
11.4.11 Interrupt Status Enable Register (IRQSTATEN)
Figure 11-13
corresponding interrupt status bit to be set by the specified event. If any bit is cleared, the corresponding
IRQSTAT bit is also cleared and is never set.
Freescale Semiconductor
Table 11-15. Relation Between Command Timeout Error and Command Complete Status
Table 11-17. Relation Between Command CRC Error and Command Timeout Error
below shows that transfer complete has higher priority than data timeout error. If both bits are
Command CRC Error
Table 11-16. Relation Between Data Timeout Error and Transfer Complete Status
shows the interrupt status enable register. Setting the bits of IRQSTATEN enables the
Transfer Complete
Command Complete
Don’t Care
0
0
1
1
0
0
1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
0
1
Command Timeout Error
Command Timeout Error
Data Timeout Error
0
1
0
1
0
0
1
0
1
X
Response not received within 64
Timeout occur during transfer
Meaning of the Status
Response Timeout Error
Meaning of the Status
Response received
Meaning of the Status
Data transfer complete
Response CRC Error
SD_CMD line conflict
SD_CLK cycles
Enhanced Secure Digital Host Controller
No error
—
—
Table 11-17
below.
11-27