MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 561

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1, ..., channel [n – 1]. The definitions of the TCD are presented as eight 32-bit values.
32-bit view of the basic TCD structure.
Figure 12-15
Table 12-16
Freescale Semiconductor
Offset DMA_Offset = 0x1000 + (32 x n ) + 0x00
Reset
Reset
31–0
Bits
0x1000 + (32 x n) + 0x01C
0x1000 + (32 x n) + 0x000
0x1000 + (32 x n) + 0x004
0x1000 + (32 x n) + 0x008
0x1000 + (32 x n) + 0x010
0x1000 + (32 x n) + 0x014
0x1000 + (32 x n) + 0x018
0x1000 + (32 x n) + 0x0C
W
W
R
R
31
15
Name
saddr
DMA Offset
describes the TCD word 0 fields.
shows the TCD word 0 field.
Source address. Memory address pointing to the source data.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 12-16. TCD Word 0 (TCDn.saddr) Field Description
Figure 12-15. TCD Word 0 (TCDn.saddr) Field
Beginning Major Iteration Count (biter)
Current Major Iteration Count (citer)
Table 12-15. TCD 32-Bit Memory Structure
(smod, ssize, dmod, dsize)
Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)
Transfer Attributes
Last Source Address Adjustment (slast)
saddr[31–16]
saddr[15–0]
All zeros
All zeros
Destination Address (daddr)
Description
Source Address (saddr)
Inner Minor Byte
Count (nbytes)
TCD Field
(bwc, major.linkch, done, active, major.e_link,
Signed Destination Address Offset (doff)
Signed Source Address Offset (soff)
e_sg, d_req, int_half, int_maj, start)
Channel Control/Status
Table 12-15
DMA Controller (DMAC)
Access: Read/Write
is a
12-17
16
0