MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 222

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Arbiter and Bus Monitor
6.2.6
The arbiter event attributes register (AEATR) reports the type of transaction that causes error that is
specified in the event register. See
AEATR is cleared only by power-on reset. The attributes of the first error event are stored. Note that this
means that AEATR does not change its value when AER is not clear. As AEATR is not affected by soft or
hard reset, software can read this register and determine the cause of the bus failure, even if the failure
caused a deadlock situation. For more information, see
Figure 6-6
Table 6-7
6-8
Offset 0x18
Reset
8–10
Bits
Bits
0–4
5–7
30
31
W
R
0
EVENT
Name
describes AEATR fields.
Name
DTO
ATO
shows the fields of AEATR.
—
—
Arbiter Event Attributes Register (AEATR)
—
Data time out. Data tenure time out interrupt mask bit.
0 Data tenure time out interrupt disabled.
1 Data tenure time out interrupt enabled.
Address time out. Address tenure time out interrupt mask bit.
0 Address tenure time out interrupt disabled.
1 Address tenure time out interrupt enabled.
Write reserved, read = 0
Event type.
000 Address time out
001 Data time out
010 Address only transfer type
011 External control word transfer type
Write reserved, read = 0
4
5
EVENT
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 6-6. Arbiter Event Attributes Register (AEATR)
7
Table 6-6. AMR Field Descriptions (continued)
8
—
Table 6-7. AEATR Field Descriptions
Section 6.2.3, “Arbiter Event Register (AER),”
10 11
MSTR_ID
All zeros
15 16
Section 6.4.2, “Error Handling Sequence.”
Description
Description
—
100 Reserved transfer type
101 Transfer error
11 c Reserved
19
TBST
20
21
TSIZE
23 24
for more information.
Freescale Semiconductor
—
Access: User read/write
26 27
TTYPE
31