MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1137

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Appendix A
Complete List of Configuration, Control, and Status
Registers
A.1
Freescale Semiconductor
Local Memory
0x040–0x063C
0x00C–0x01C
0x088–0x09C
0x068-0x07C
Offset (Hex)
0x02C
0x03C
0x0A0
0x0A4
0x000
0x004
0x008
0x020
0x024
0x028
0x030
0x034
0x038
0x064
0x080
0x084
Local Access Windows
Internal memory map base address register (IMMRBAR)
Reserved
Alternate configuration base address register (ALTCBAR)
Reserved
eLBC local access window 0 base address register
(LBLAWBAR0)
eLBC local access window 0 attribute register (LBLAWAR0)
eLBC local access window 1 base address register
(LBLAWBAR1)
eLBC local access window 1 attribute register (LBLAWAR1)
eLBC local access window 2 base address register
(LBLAWBAR2)
eLBC local access window 2 attribute register (LBLAWAR2)
eLBC local access window 3 base address register
(LBLAWBAR3)
eLBC local access window 3 attribute register (LBLAWAR3)
Reserved
Reserved
Reserved
PCI Express local access window base address register
(PCIEXP1LAWBAR)
PCI Express local access window attribute register
(PCIEXP1LAWAR)
Reserved
DDR2 local access window 0 base address register
(DDRLAWBAR0)
DDR2 local access window 0 attribute register
(DDRLAWAR0)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table A-1. Local Access Register Memory Map
Local Access—Block Base Address 0x0_000
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xFF40_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
—
—
1
2
3
4
Section/Page
5.1.4.6/5-10
5.1.4.7/5-11
5.1.4.8/5-12
5.1.4.1/5-5
5.1.4.2/5-7
5.1.4.3/5-7
5.1.4.4/5-8
5.1.4.3/5-7
5.1.4.4/5-8
5.1.4.3/5-7
5.1.4.4/5-8
5.1.4.3/5-7
5.1.4.4/5-8
5.1.4.5/5-9
—
—
—
—
—
—
A-1