MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet
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MPC8308 PowerQUICC II Pro Processor Reference Manual MPC8308RM Rev. 0 4/2010 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-16 1.2.13 System Timers ........................................................................................................... 1-17 2.1 Signals Overview ............................................................................................................. 2-1 2.2 Output Signal States During Reset ................................................................................ 2-20 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title About This Book Chapter 1 Overview Chapter 2 Signal Descriptions ...
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... Inbound Address Translation and Mapping Windows .............................................. 5-14 5.1.10 Internal Memory Map................................................................................................ 5-14 5.1.11 Accessing Internal Memory from External Masters.................................................. 5-15 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Contents Title Chapter 4 Reset, Clocking, and Initialization Chapter 5 System Configuration Page Number Freescale Semiconductor ...
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... Initialization/Application Information (Programming Guidelines for GTM Registers).... 5-68 5.7 Power Management Control (PMC) .............................................................................. 5-68 5.7.1 External Signal Description ....................................................................................... 5-69 5.7.2 PMC Memory Map/Register Definition .................................................................... 5-69 5.7.3 Functional Description............................................................................................... 5-70 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Page Number v ...
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... Instruction Set and Addressing Modes ...................................................................... 7-26 7.4.3 Cache Implementation ............................................................................................... 7-29 7.4.4 Interrupt Model .......................................................................................................... 7-31 7.4.5 Memory Management................................................................................................ 7-35 7.4.6 Instruction Timing ..................................................................................................... 7-36 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Contents Title Chapter 6 Arbiter and Bus Monitor Chapter 7 e300 Processor Core Overview Page Number Freescale Semiconductor ...
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... System Error Force Register (SERFR) ...................................................................... 8-29 8.5.22 System Critical Interrupt Vector Register (SCVCR) ................................................. 8-29 8.5.23 System Management Interrupt Vector Register (SMVCR) ....................................... 8-30 8.6 Functional Description................................................................................................... 8-31 8.6.1 Interrupt Types ........................................................................................................... 8-31 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Chapter 8 Page Number vii ...
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... Error Checking and Correcting (ECC) ...................................................................... 9-57 9.5.12 Error Management ..................................................................................................... 9-59 9.6 Initialization/Application Information ........................................................................... 9-59 9.6.1 DDR SDRAM Initialization Sequence ...................................................................... 9-61 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 viii Contents Title Chapter 9 DDR Memory Controller Chapter 10 Enhanced Local Bus Controller Page Number Freescale Semiconductor ...
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... Interrupt Status Enable Register (IRQSTATEN) ..................................................... 11-27 11.4.12 Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 11-30 11.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 11-32 11.4.14 Host Controller Capabilities (HOSTCAPBLT) ....................................................... 11-34 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Chapter 11 Enhanced Secure Digital Host Controller Page Number ix ...
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... DMA Clear Interrupt Request (DMACINT) ........................................................... 12-10 12.3.5 DMA Clear Error (DMACERR).............................................................................. 12-11 12.3.6 DMA Set START Bit (DMASSRT)......................................................................... 12-11 12.3.7 DMA Clear DONE Status (DMACDNE)................................................................ 12-12 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Contents Title Chapter 12 DMA Controller (DMAC) Page Number Freescale Semiconductor ...
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... Functional Description................................................................................................. 13-44 13.4.1 System Interface ...................................................................................................... 13-44 13.4.2 DMA Engine............................................................................................................ 13-45 13.4.3 FIFO RAM Controller ............................................................................................. 13-45 13.4.4 PHY Interface .......................................................................................................... 13-45 13.5 Host Data Structures .................................................................................................... 13-46 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Chapter 13 Universal Serial Bus Interface Page Number xi ...
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... Device Operation ................................................................................................... 13-153 13.9.3 Non-Zero Fields the Register File ......................................................................... 13-154 13.9.4 SOF Interrupt ......................................................................................................... 13-154 13.9.5 Embedded Design .................................................................................................. 13-154 13.9.6 Miscellaneous Variations from EHCI .................................................................... 13-154 13.10 Timing Diagrams ....................................................................................................... 13-156 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xii Contents Title Page Number Freescale Semiconductor ...
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... Interrupts............................................................................................................... 14-121 14.6.3 Mailbox .................................................................................................................. 14-123 14.6.4 Power Management ............................................................................................... 14-125 14.6.5 Hot Reset................................................................................................................ 14-126 14.7 Initialization/Application Information ....................................................................... 14-126 14.7.1 Initialization Sequence........................................................................................... 14-126 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Chapter 14 PCI Express Interface Controller Page Number xiii ...
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... Memory-Mapped Register Descriptions.................................................................. 16-21 16.6 Functional Description............................................................................................... 16-120 16.6.1 Connecting to Physical Interfaces on Ethernet ...................................................... 16-121 16.6.2 Gigabit Ethernet Controller Channel Operation .................................................... 16-124 16.6.3 TCP/IP Off-Load ................................................................................................... 16-139 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xiv Contents Title Chapter 15 SerDes PHY Chapter 16 Page Number Freescale Semiconductor ...
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... Generation of SCL When SDA is Negated ............................................................. 17-24 17.5.8 Slave Mode Interrupt Service Routine..................................................................... 17-24 18.1 Overview........................................................................................................................ 18-1 18.1.1 Features...................................................................................................................... 18-2 18.1.2 Modes of Operation ................................................................................................... 18-2 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Chapter Interface Chapter 18 DUART Page Number ...
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... External Signal Descriptions ..................................................................................... 20-2 20.3 JTAG Registers and Scan Chains .................................................................................. 20-3 21.1 Introduction.................................................................................................................... 21-1 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xvi Contents Title Chapter 19 Serial Peripheral Interface Chapter 20 JTAG/Testing Support Chapter 21 General Purpose I/O (GPIO) Page Number Freescale Semiconductor ...
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... A.20 Enhanced Three-Speed Ethernet Controllers (eTSECs) ............................................... A-21 A.21 SerDes PHY .................................................................................................................. A-31 A.22 Enhanced Secure Digital Host Controller (eSDHC)..................................................... A-32 A.23 Universal Serial Bus (USB) Interface........................................................................... A-32 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Contents Title Appendix A Page Number xvii ...
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... Paragraph Number MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xviii Contents Title Page Number Freescale Semiconductor ...
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... System I/O Configuration Register Low (SICRL) ............................................................... 5-20 5-15 System I/O Configuration Register High (SICRH) .............................................................. 5-22 5-16 DDR Control Driver Register (DDRCDR) ........................................................................... 5-26 5-17 DDR Debug Status Register (DDRDSR).............................................................................. 5-27 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Figu res Page Number xix ...
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... Power Management Controller Configuration Register ....................................................... 5-69 6-1 Arbiter Configuration Register (ACR) ................................................................................... 6-3 6-2 Arbiter Timers Register (ATR) ............................................................................................... 6-4 6-3 Arbiter Event Register (AER)................................................................................................. 6-5 6-4 Arbiter Interrupt Definition Register (AIDR) ......................................................................... 6-6 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... System Management Interrupt Vector Register (SMVCR)................................................... 8-30 8-28 Interrupt Structure ................................................................................................................. 8-32 8-29 DDR Interrupt Request Masking .......................................................................................... 8-39 8-30 Message Shared Interrupt Register (MSIRs) ........................................................................ 8-41 8-31 Message Shared Interrupt Mask Register (MSIMR) ............................................................ 8-41 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxi ...
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... DDR SDRAM Clock Distribution Example for ¥8 DDR SDRAMs .................................... 9-49 9-38 DDR SDRAM Mode-Set Command Timing ........................................................................ 9-50 9-39 Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-51 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxii Figures Title Page Number Freescale Semiconductor ...
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... Enhanced Local Bus to GPCM Device Interface................................................................ 10-42 10-33 GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8).............. 10-43 10-34 GPCM General Read Timing Parameters ........................................................................... 10-43 10-35 GPCM General Write Timing Parameters .......................................................................... 10-45 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxiii ...
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... Memory Refresh Timer Request Block Diagram ............................................................... 10-70 10-61 UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 10-73 10-62 UPM Clock Scheme for LCRR[CLKDIV ........................................................... 10-74 10-63 RAM Array and Signal Generation .................................................................................... 10-74 10-64 RAM Word Fields ............................................................................................................... 10-75 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxiv Figures Title Page Number Freescale Semiconductor ...
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... Card Interrupt Scheme; b) Card Interrupt Detection and Handling Procedure .............. 11-45 11-26 Flow Diagram for Card Detection ...................................................................................... 11-47 11-27 Flow Chart for Reset of eSDHC and SD I/O Card ............................................................. 11-48 12-1 DMA Block Diagram............................................................................................................ 12-1 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxv ...
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... Current Asynchronous List Address (ASYNCLISTADDR) .............................................. 13-19 13-15 Endpoint List Address (ENDPOINTLISTADDR).............................................................. 13-20 13-16 Master Interface Data Burst Size (BURSTSIZE) ............................................................... 13-21 13-17 Transmit FIFO Tuning Controls (TXFILLTUNING) ......................................................... 13-22 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxvi Figures Title Page Number Freescale Semiconductor ...
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... Example Host Controller Traversal of Recovery Path via FSTNs...................................... 13-96 13-56 Split Transaction State Machine for Interrupt..................................................................... 13-99 13-57 Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 13-106 13-58 siTD Scheduling Boundary Examples .............................................................................. 13-108 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxvii ...
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... PCI Express Secondary Bus Number Register ................................................................... 14-28 14-25 PCI Express Subordinate Bus Number Register................................................................. 14-28 14-26 PCI Express I/O Base Register ........................................................................................... 14-29 14-27 PCI Express I/O Limit Register .......................................................................................... 14-29 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxviii Figures Title Page Number Freescale Semiconductor ...
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... PCI Express Extended Configuration Space....................................................................... 14-52 14-66 PCI Express Advanced Error Reporting Capability ID Register ........................................ 14-53 14-67 PCI Express Uncorrectable Error Status Register............................................................... 14-53 14-68 PCI Express Uncorrectable Error Mask Register ............................................................... 14-54 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxix ...
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... PCI Express Read DMA Status Register (PEX_RDMA_STAT)........................................ 14-86 14-108 PCI Express Outbound Mailbox Control Register (PEX_OMBCR) .................................. 14-87 14-109 MPCI Express Outbound Mailbox Data Register (PEX_OMBDR) ................................... 14-88 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxx Figures Title Page Number Freescale Semiconductor ...
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... PCI Express High-Level Layering .....................................................................................14-111 14-139 PCI Express Packet Flow ...................................................................................................14-111 14-140 Outbound Byte Swapping ................................................................................................. 14-114 14-141 Example—How to Generate WAKE#............................................................................... 14-126 14-142 DMA Descriptor Format ................................................................................................... 14-128 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxxi ...
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... Receive Queue Filer Table Property IDs 0, 2–15 Register Definition................................ 16-55 16-30 Receive Queue Filer Table Property ID1 Register Definition ............................................ 16-56 16-31 MRBLR Register Definition ............................................................................................... 16-59 16-32 RBPTR0–RBPTR7 Register Definition .............................................................................. 16-60 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxxii Figures Title Page Number Freescale Semiconductor ...
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... Receive Undersize Packet Counter Register Definition ..................................................... 16-87 16-71 Receive Oversize Packet Counter Register Definition ....................................................... 16-87 16-72 Receive Fragments Counter Register Definition ................................................................ 16-88 16-73 Receive Jabber Counter Register Definition....................................................................... 16-88 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxxiii ...
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... TMR_CNT_H Register Definition ................................................................................... 16-116 16-110 TMR_ADD Register Definition........................................................................................ 16-116 16-111 TMR_ACC Register Definition ........................................................................................ 16-117 16-112 TMR_PRSC Register Definition ...................................................................................... 16-117 16-113 TMROFF_H/L Register Definition .................................................................................. 16-118 16-114 TMR_ALARM1-2_H/L Register Definition .................................................................... 16-118 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxxiv Figures Title Page Number Freescale Semiconductor ...
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... Interrupt Enable Registers (UIER1 and UIER2)................................................................... 18-8 18-7 Interrupt ID Registers (UIIR1 and UIIR2)............................................................................ 18-9 18-8 FIFO Control Registers (UFCR1 and UFCR2)................................................................... 18-10 18-9 Line Control Register (ULCR1 and ULCR2) ..................................................................... 18-11 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figures Title Page Number xxxv ...
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... GPIO Data Register (GPDAT) .............................................................................................. 21-4 21-5 GPIO Interrupt Event Register (GPIER) .............................................................................. 21-4 21-6 GPIO Interrupt Mask Register (GPIMR).............................................................................. 21-5 21-7 GPIO Interrupt Control Register (GPICR) ........................................................................... 21-5 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxxvi Figures Title Page Number Freescale Semiconductor ...
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... RCER Bit Settings ................................................................................................................ 4-29 4-30 Clock Configuration Registers Memory Map....................................................................... 4-29 4-31 System PLL Mode Register Bit Settings .............................................................................. 4-30 4-32 OCCR Bit Settings ................................................................................................................ 4-31 4-33 SCCR Bit Descriptions ......................................................................................................... 4-32 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Tables Page Number xxxvii ...
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... SWSRR Bit Settings ............................................................................................................. 5-35 5-37 RTC External Signals............................................................................................................ 5-40 5-38 RTC Register Address Map .................................................................................................. 5-40 5-39 RTCNR Bit Settings.............................................................................................................. 5-41 5-40 RTLDR Bit Settings .............................................................................................................. 5-42 5-41 RTPSR Bit Settings ............................................................................................................... 5-42 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xxxviii Tables Title Page Number Freescale Semiconductor ...
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... Reserved Transaction Type Encoding................................................................................... 6-16 6-12 Illegal Transaction Type Encoding ....................................................................................... 6-16 7-1 Device Revision Level Cross-Reference .............................................................................. 7-13 7-2 MSR Bit Descriptions ........................................................................................................... 7-18 7-3 e300 HID0 Bit Descriptions.................................................................................................. 7-22 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xxxix ...
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... SERFR Field Descriptions .................................................................................................... 8-29 8-32 SCVCR Field Descriptions ................................................................................................... 8-30 8-33 SMVCR Field Descriptions .................................................................................................. 8-31 8-34 Interrupt Source Priority Levels............................................................................................ 8-34 8-35 Message Shared Registers Address Map .............................................................................. 8-40 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...
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... CAPTURE_ATTRIBUTES Field Descriptions .................................................................... 9-36 9-34 CAPTURE_ADDRESS Field Descriptions .......................................................................... 9-37 9-35 ERR_SBE Field Descriptions ............................................................................................... 9-37 9-36 Byte Lane to Data Relationship ............................................................................................ 9-41 9-37 Supported DDR2 SDRAM Device Configurations .............................................................. 9-42 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xli ...
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... FMR Field Descriptions...................................................................................................... 10-33 10-25 FIR Field Descriptions ........................................................................................................ 10-35 10-26 FCR Field Descriptions....................................................................................................... 10-35 10-27 FBAR Field Descriptions.................................................................................................... 10-36 10-28 FPAR Field Descriptions, Small Page Device (ORx[PGS] = 0)......................................... 10-37 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xlii Tables Title Page Number Freescale Semiconductor ...
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... IRQSTAT Field Descriptions .............................................................................................. 11-24 11-15 Relation Between Command Timeout Error and Command Complete Status ................... 11-27 11-16 Relation Between Data Timeout Error and Transfer Complete Status ............................... 11-27 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xliii ...
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... ULPI Signal Descriptions ..................................................................................................... 13-3 13-3 USB Interface Memory Map................................................................................................. 13-4 13-4 CAPLENGTH Register Field Descriptions .......................................................................... 13-7 13-5 HCIVERSION Register Field Descriptions.......................................................................... 13-7 13-6 HCSPARAMS Register Field Descriptions .......................................................................... 13-7 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xliv Tables Title Page Number Freescale Semiconductor ...
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... Buffer Pointer Page 1 (Plus) ........................................................................................ 13-51 13-44 Buffer Pointer Page 2 (Plus) ............................................................................................... 13-51 13-45 Buffer Pointer Page 3–6 ...................................................................................................... 13-52 13-46 Next Link Pointer................................................................................................................ 13-52 13-47 Endpoint and Transaction Translator Characteristics ......................................................... 13-53 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xlv ...
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... Device Controller Stall Response Matrix ......................................................................... 13-135 13-86 Variable Length Transfer Protocol Example (ZLT = 0) .................................................... 13-137 13-87 Variable Length Transfer Protocol Example (ZLT = 1) .................................................... 13-137 13-88 Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 13-138 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xlvi Tables Title Page Number Freescale Semiconductor ...
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... PCI Express Memory Limit Register Fields Description ................................................... 14-31 14-30 PCI Express Prefetchable Memory Base Register Fields Description ............................... 14-32 14-31 PCI Express Prefetchable Memory Limit Register Fields Description .............................. 14-32 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xlvii ...
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... PCI Express Header Log Register Fields Description ........................................................ 14-59 14-71 PCI Express Root Error Command Register Fields Description ........................................ 14-60 14-72 PCI Express Root Error Status Register Fields Description ............................................... 14-61 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 xlviii Tables Title Page Number Freescale Semiconductor ...
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... PEX_IMBDR Register Fields Description ......................................................................... 14-89 14-110 PEX_HIER Register Fields Description ............................................................................. 14-90 14-111 PEX_HISR Register Fields Description ............................................................................. 14-91 14-112 PEX_HOPIVR Register Fields Description ....................................................................... 14-92 14-113 PEX_HIPIVR Register Fields Description ......................................................................... 14-92 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number xlix ...
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... SRDSCR4 Field Descriptions ............................................................................................... 15-9 15-8 SRDSRSTCTL Field Descriptions ..................................................................................... 15-10 16-1 eTSECn Network Interface Signal Properties ...................................................................... 16-6 16-2 eTSEC Signals—Detailed Signal Descriptions .................................................................... 16-7 16-3 Module Memory Map Summary......................................................................................... 16-10 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Tables Title Page Number Freescale Semiconductor ...
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... MACCFG1 Field Descriptions ........................................................................................... 16-64 16-40 MACCFG2 Field Descriptions ........................................................................................... 16-66 16-41 IPGIFG Field Descriptions ................................................................................................. 16-68 16-42 HAFDUP Field Descriptions .............................................................................................. 16-69 16-43 MAXFRM Field Descriptions ............................................................................................ 16-70 16-44 MIIMCFG Field Descriptions............................................................................................. 16-70 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number li ...
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... TPKT Field Descriptions .................................................................................................... 16-90 16-81 TMCA Field Descriptions................................................................................................... 16-90 16-82 TBCA Field Descriptions.................................................................................................... 16-91 16-83 TXPF Field Descriptions .................................................................................................... 16-91 16-84 TDFR Field Descriptions .................................................................................................... 16-92 16-85 TEDF Field Descriptions .................................................................................................... 16-92 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 lii Tables Title Page Number Freescale Semiconductor ...
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... TMR_ALARMn_H/L Register Field Descriptions .......................................................... 16-119 16-123 TMR_FIPER Register Field Descriptions ........................................................................ 16-120 16-124 TMR_ETTS1-2_H Register Field Descriptions ............................................................... 16-120 16-125 RGMII and MII Signals Multiplexing .............................................................................. 16-123 16-126 Shared Signals................................................................................................................... 16-123 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number liii ...
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... I2CDFSRR Field Descriptions............................................................................................ 17-10 18-1 DUART Signal Overview ..................................................................................................... 18-3 18-2 DUART Signals—Detailed Signal Descriptions .................................................................. 18-3 18-3 DUART Register Summary .................................................................................................. 18-4 18-4 URBR Field Descriptions ..................................................................................................... 18-5 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 liv Tables Title Page Number Freescale Semiconductor ...
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... GPIMR Bit Settings .............................................................................................................. 21-5 21-8 GPICR Bit Settings ............................................................................................................... 21-5 A-1 Local Access Register Memory Map..................................................................................... A-1 A-2 System Configuration Registers............................................................................................. A-2 A-3 Watchdog Timer (WDT) Registers ........................................................................................ A-3 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Tables Title Page Number lv ...
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... A-21 Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers ...................................... A-21 A-22 SerDes PHY Registers ......................................................................................................... A-31 A-23 Enhanced Secure Digital Host Controller (eSDHC) Registers ............................................ A-32 A-24 USB Interface Registers....................................................................................................... A-32 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 lvi Tables Title Page Number Freescale Semiconductor ...
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... Chapter 8, “Integrated Programmable Interrupt Controller (IPIC),” protocol, various types of interrupt sources controlled by the IPIC unit, and the IPIC registers with MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor provides a high-level description of features and functionality of the provides a listing of all the external signals, cross-references for describes the memory map of the device ...
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... PCI Express interface controller, describes the block which includes the serializer/deserializer PHY, the describes the inter-IC (IIC or I describes the two enhanced 2 C) bus controllers of the device. These 2 C controllers to initialize Freescale Semiconductor ...
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... AC, DC, and thermal characteristics, as well as other design considerations. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor describes the (dual) universal asynchronous receiver/transmitters describes the MPC8308 serial peripheral interface (SPI) describes the joint test action group (JTAG) interface of the ...
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... Indicates a read-only bit field in a memory-mapped register. R FIELDNAME W Indicates a write-only bit field in a memory-mapped register. Although these bits R can be written to as ones or zeros, they are always read as zeros. W FIELDNAME Signal Conventions OVERBAR An overbar indicates that a signal is active-low. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev Freescale Semiconductor ...
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... Frame-check sequence GMII Gigabit media independent interface GPCM General-purpose chip-select machine GPIO General-purpose I/O GPR General-purpose register GTM General purpose timers IAD Internet access device MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table i. Acronyms and Abbreviated Terms Meaning lxi ...
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... Peripheral component interconnect PCS Physical coding sublayer PIC Programmable interrupt controller PIT Periodic interval timer PKEU Public key execution unit PMA Physical medium attachment PMD Physical medium dependent POR Power-on reset MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 lxii Meaning Freescale Semiconductor ...
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... Translation lookaside buffer TSEC Three-speed Ethernet controller Tx Transmit TxBD Transmit buffer descriptor UART Universal asynchronous receiver/transmitter UPM User-programmable machine UTP Unshielded twisted pair WDT Watchdog timer ZBT Zero bus turnaround MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Meaning lxiii ...
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... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 lxiv Freescale Semiconductor ...
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... Enhanced Express Secure Digital Host Controller The major features of this device are as follows: • e300c3 processor core MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor 2 C controllers, dual UART (DUART), GPIOs, Figure 1-1. e300c3 Core with Power Management 16-KB 16-KB ...
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... TCP/IP acceleration and QoS features available – and IP v6 header recognition on receive – header checksum verification and generation – TCP and UDP checksum verification and generation MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-2 Freescale Semiconductor ...
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... SerDes, PHY, and controllers • PCI Express — Supports one interface supporting ×1 width — Compatible with the PCI Express 1.0a Specification — Selectable operation as root complex or endpoint — 32- and 64-bit addressing MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview 1-3 ...
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... External and internal interrupts directed to host processor — Supports MSI functionality for PCI Express — Unique vector number for each interrupt source 2 • Two I C interfaces — Two-wire interface — Multiple-master support MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-4 Freescale Semiconductor ...
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... Card bus clock frequency MHz — Supports 1-/4-bit SD and SDIO modes, – 200 Mbps of data transfer for SD/SDIO/MMC cards using four parallel data lines — Supports single- and multi-block read and write MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview 1-5 ...
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... An alarm function with programmable and maskable alarm interrupt — Programmable and maskable every second interrupt — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock — RTC function can be disabled, if required MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-6 Freescale Semiconductor ...
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... As an added feature to the e300 core, the device can lock the contents of three of the four ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview 1-7 ...
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... The e300 core has high-performance 64-bit data bus and 32-bit address bus interfaces to the rest of the device. The e300 core supports single-beat and burst data transfers for memory accesses and memory-mapped I/O operations. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-8 Freescale Semiconductor ...
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... Power Time Base Dissipation Counter/ Control Decrementer JTAG/COP Clock Multiplier Interface Figure 1-2. MPC8308 Integrated e300c3 Core Block Diagram MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor 64-Bit Sequential Fetcher 64-Bit Instruction Queue Dispatch Unit 64-Bit 32-Bit 64-Bit Load/Store Unit ...
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... TCP/UDP payload checksum verification including verification of associated pseudo-header checksums. On transmit, the eTSEC provides IP v4 and TCP/UDP header checksum generation. The eTSEC does not checksum transmitted packets with IP header options or IP fragments. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-10 Freescale Semiconductor ...
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... The USB 2.0 controller offers operation as a host or device. The USB controller provides point-to-point connectivity, which complies with the Universal Serial Bus Revision 2.0 Specification. The USB controllers can be configured to operate as a stand-alone host or stand-alone device. See more information. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview Figure 1-3 for 1-11 ...
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... NAND Flash control machine (FCM), a general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-12 CSB Dual-Role Module (DR) Figure 1-3. USB Controllers Port Configuration TX Buffer RX Buffer Freescale Semiconductor ...
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... Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during Flash reads and programming — Interrupt-driven block transfer for reads and writes — Programmable command and data transfer sequences eight steps supported — Generic command and address registers support proprietary Flash interfaces MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview 1-13 ...
Page 78
... IPIC can support external interrupt request with programmable triggering mechanism. It can be programmed to use one of the following mechanisms: — Active low level triggering — Active high level triggering — Raising edge triggering — Falling edge triggering MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-14 Freescale Semiconductor ...
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... Single design with two channels (Tx and Rx) • 32-byte transfer control descriptor per channel stored in local memory • 32 bytes of data registers, used as temporary storage to support burst transfers MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor 2 C controller consists unit supports general broadcast mode and Overview ...
Page 80
... MMC cards or downloadable from cellular phones, WLAN, or other wireless networks. • Secure digital (SD) card The secure digital (SD) card is an evolution of old MMC technology specifically designed to meet the security, capacity, performance, and environment requirements inherent in the emerging MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-16 16 – 1) and Freescale Semiconductor ...
Page 81
... Periodic interrupt timer • Real time clock • Software watchdog timer • One general-purpose timer block, supporting four 16-bit programmable timers or two cascaded 32-bit timers, or one cascaded 64-bit counter MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Overview 1-17 ...
Page 82
... Overview MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 1-18 Freescale Semiconductor ...
Page 83
... Note that individual chapters of this document provide details for each signal, describing each signal’s behavior when asserted and negated and when the signal is an input or an output. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor NOTE • IPIC interface signals • ...
Page 84
... IRQ[3]/ CKSTOP_IN SPIMOSI /MSRCID4/LSRCID4 SPIMISO /MDVAL/LDVAL SPICLK SPISEL TCK TDI TDO TMS TRST UART_SOUT[1]/MSRCID0/LSRCID0 UART_SOUT[2]/MSRCID2/LSRCID2 UART_SIN[1]/MSRCID1/LSRCID1 UART_SIN[2]/MSRCID3/LSRCID3 Freescale Semiconductor eTSEC1 Ethernet Interface 17 Signals Ethernet Mgmt Interface 2 Signals Enhanced Local Bus Interface 56 Signals IPIC Interface 4 Signals SPI Interface ...
Page 85
... Description MDQ[0:31] DDR data MECC[0:7] DDR ECC data MDM[0:3] DDR data mask MDM[8] DDR data mask MDQS[0:3] DDR data strobe MDQS[8] DDR data strobe MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor USBDR_PWR_FAULT 1 USBDR_CLK 1 1 USBDR_DIR 1 1 USBDR_NXT 1 1 USBDR_TXDRXD[0:7] 8 ...
Page 86
... TSEC1_GTX_ 16-2/16-7 CLK125 CFG_RESET_ 4-1/4-1 SOURCE[0:3] LBC_PM_REF_10 — Freescale Semiconductor ...
Page 87
... General-purpose I/O signal GPIO[1] General-purpose I/O signal GPIO[2] General-purpose I/O signal GPIO[3] General-purpose I/O signal GPIO[4] General-purpose I/O signal MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eTSEC1 1 I/O 16-2/16-7 eTSEC1 1 I 16-2/16-7 ...
Page 88
... Function(s) Page — — TSEC2_RXD[0] 16-2/16-7 TSEC2_RX_ER 16-2/16-7 TSEC2_TX_CLK/ 16-2/16-7 TSEC2_GTX_CLK125 TSEC2_TXD[3:0] 16-2/16-7 TSEC2_TX_EN 16-2/16-7 — — GPIO[8] 21-1/21-2 — — GPIO[13] 21-1/21-2 — — GPIO[14] 21-1/21-2 GPIO[11:12] 21-1/21-2 GPIO[1] 21-1/21-2 GPIO[2] 21-1/21-2 GPIO[3] 21-1/21-2 GPIO[4] 21-1/21-2 — — Freescale Semiconductor ...
Page 89
... Serial receiver, lane A, positive data RXA Serial receiver, lane A, negative data (complement) SD_IMP_CAL_RX Receiver impedance control signal SD_REF_CLK SerDes PLL reference clock MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page USB 1 I 13-2/13-3 USB 1 I ...
Page 90
... Table/ Function(s) Page — — — — — — — — — — — — — — — — — — — — TSEC1_TX_ER 16-2/16-7 TSEC1_TX_EN 16-2/16-7 — — — — — — — — — — — — Freescale Semiconductor ...
Page 91
... UART_SIN[2] DUART serial data in SPIMOSI SPI master-out slave-in SPIMISO SPI master-in slave-out SPICLK SPI clock SPISEL SPI slave select MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eLBC 1 O 10-2/10-5 eLBC 1 O 10-2/10-5 ...
Page 92
... GPIO[16] 21-1/21-2 GPIO[17] 21-1/21-2 GTM1_TIN1/ 5-53/5-55/ GPIO[18] 21-1/21-2 Freescale Semiconductor — — — — — — — — — — — — — — — — — — ...
Page 93
... Memory debug source ID MSRCID2/LSRCID2 Memory debug source ID MSRCID3/LSRCID3 Memory debug source ID MSRCID4/LSRCID4 Memory debug source ID MDVAL/LDVAL Memory debug data valid MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eSDHC 1 I/O 11-1/11-4 eSDHC 1 I/O ...
Page 94
... IIC_SDA2/IRQ2 17-1/17-3, 8-1/8-5 TSEC2_COL 16-2/16-7 TSEC2_TX_ER 16-2/16-7 TSEC2_TX_CLK/ 16-2/16-7 TSEC2_GTX_CLK125 TSEC2_TXD[3:0] 16-2/16-7 TSEC2_TX_EN 16-2/16-7 TSEC2_GTX_CLK 16-2/16-7 TSEC2_RX_CLK 16-2/16-7 TSEC2_RX_DV 16-2/16-7 — TSEC2_RXD[0] 16-2/16-7 TSEC2_RX_ER 16-2/16-7 SD_WP/GPIO[19] 11-1/11-4/ 21-1/21-2 SD_DAT[3]/GPIO[23] 11-1/11-4/ 21-1/21-2 — Freescale Semiconductor — — — — ...
Page 95
... LBCTL LBC data buffer control LCLK0 LBC clock LCS[0:3] LBC chip select 0–3 LD[0:15] LBC data MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page Global Timers 1 I/O 5-53/5-55 Global Timers ...
Page 96
... Page — — — — — — — — — — — — — — — — — — — — — — — — — — — — IRQ[1] 8-1/8-5 — — — — — — — — Freescale Semiconductor ...
Page 97
... Serial receiver, lane A, negative data (complement) SD_CD Card detection signal SD_CLK eSDHC clock out SD_CMD eSDHC command/ response signals SD_DAT[0] Data signal 0 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page DDR2 4 I/O 9-1/9-4 DDR2 1 ...
Page 98
... GTM1_TGATE1/ 5-53/5-55/ GPIO[19] 21-1/21-2 — — — — — MDVAL/LDVAL 10-2/10-5 MSRCID4/LSRCID4 10-2/10-5 — — — — — Freescale Semiconductor — — — — — — — — — —, —, — — — — — ...
Page 99
... TSEC1_MDC Ethernet management data clock TSEC1_MDIO Ethernet management data in/out TSEC1_RX_CLK eTSEC1 receive clock TSEC1_RX_DV eTSEC1 receive data valid MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page JTAG 1 O 20-1/20-2 Test 1 I Misc ...
Page 100
... Page — — — — GPIO[3] 21-1/21-2 GPIO[4] 21-1/21-2 TSEC1_GTX_ 16-2/16-7 CLK125 LBC_PM_REF_10 — LB_POR_CFG_ — BOOT_ECC CFG_RESET_ 4-1/4-1 SOURCE[0:3] GPIO[0] 21-1/21-2 GPIO[0] 21-1/21-2 GPIO[2] 21-1/21-2 GPIO[10]/ 21-1/21-2/ TSEC2_TX_CLK GPIO[3] 21-1/21-2 GPIO[4] 21-1/21-2 GPIO[9] 21-1/21-2 GPIO[8] 21-1/21-2 GPIO[5:7] 21-1/21-2 Freescale Semiconductor ...
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... Direction of data bus USBDR_NXT Nest data USBDR_PCTL[0:1] Port control 0–1 USBDR_PWR_FAULT USB VBus power fault USBDR_STP End of a transfer on the bus MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Functional No. of Table/ I/O Block Signals Page eTSEC 1 I/O 16-2/16-7 eTSEC ...
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... State During Reset High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Driven Low Low Low Driven Low High-Z Active—used to load reset configuration word Freescale Semiconductor Table/ Page — — — — — ...
Page 103
... SD_CLK SD_PLL_TPD TDO QUIESCE GTM1_TOUT[3:4] USBDR_PCTL[0:1] USBDR_STP MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Signal LBC chip select 0 LBC chip select LBC write enable LBC data buffer control LBC output enable/GP line 2 LBC clock 0 LBC UPM General purpose line ...
Page 104
... Signal Descriptions MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 2-22 Freescale Semiconductor ...
Page 105
... This would allow for maintaining the legacy functionality when set to zero. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Section 5.1.4.1, “Internal Memory Map Registers Base Address 3-1 ...
Page 106
... Kbytes — 4 Kbytes 9.4/9-9 256 bytes 17.3/17-4 256 bytes 4.8 Kbytes — 4 Kbytes 18.3/18-3 2.3 Kbytes — 4 Kbytes 10.3/10-7 4 Kbytes — 4 Kbytes 19.3/19-7 4 Kbytes — 4 Kbytes 14.3/14-5 102.4 Kbytes — 4 Kbytes 13.3/13-4 Freescale Semiconductor ...
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... DMAC 0x2_E000–0x2_FFFF eSDHC 0x2_F000–0xE_2FFF Reserved 0xE_3000–0xE_30FF SerDes 0xE_3100–0xF_FFFF Reserved MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 3-1. IMMR Memory Map (continued) Block Actual Size 4 Kbytes 4 Kbytes — 8 Kbytes 8 Kbytes — — — ...
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... Memory Map MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 3-4 Freescale Semiconductor ...
Page 109
... Requirements An open-drain signal. An external pull-up is required. Reset State Output, driven low during power-on and hard reset flows. High impedance after reset MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Section 4.3.2, “Reset Configuration Words,” Table 4-1. System Control Signals Description Negated— ...
Page 110
... Negation - Must be asserted for at least 2 SYS_CLK_IN cycles. they are defined in detail in their respective chapters. Table 4-2. External Clock Signals Description Timing Assertion/Negation—For timing information, see PowerQUICC II Pro MPC8308 Hardware Specification . Timing Assertion/Negation—For timing information, see PowerQUICC II Pro MPC8308 Hardware Specification . Freescale Semiconductor ...
Page 111
... After the device CSB bus monitor reaches a timeout condition, a bus monitor reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 4-2. External Clock Signals (continued) Timing Assertion/Negation—For timing information, see PowerQUICC II Pro MPC8308 Hardware Specification . Section 4.5.1.3, “ ...
Page 112
... Table 4-3. Reset Causes (continued) Description Table 4-4. Reset Actions Reset Source External Hard Reset Software Watchdog Power-On Reset Software Hard Reset Yes Yes Yes Yes Yes Yes No No Bus Monitor SRESET Checkstop No No Yes No Yes No Yes No Yes No Yes No No Yes No No Freescale Semiconductor ...
Page 113
... If the e300 core is required to proceed, the boot sequencer should enable boot vector fetch by clearing ACR[COREDIS] as described in 14. The boot vector fetch by the core can proceed, if enabled. The device is now in its ready state. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Reset, Clocking, and Initialization Section 6.2.1, “Arbiter Configuration Register (ACR).” 4-5 ...
Page 114
... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 4-6 Start loading reset configuration words Figure 4-1. Power-On Reset Flow NOTE Section 4.3.3, “Loading the Reset NOTE PLLs are locked (no external indication) End loading reset configuration words. Duration depends on source Freescale Semiconductor ...
Page 115
... PowerQUICC II Pro MPC8308 Hardware Specification. This section describes the modes configured by the reset configuration signals. Note that the reset configuration input sampled values are accessible to software through memory-mapped registers, as MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Stable clock Start loading reset configuration words Figure 4-2 ...
Page 116
... Hard-coded option 2. Reset configuration word is not loaded. Hard-coded option 3. Reset configuration word is not loaded. Hard-coded option 4. Reset configuration word is not loaded. Reserved Reserved Reserved and Section 4.5.2.1, “System PLL Mode 4-5, select whether the device loads a reset Meaning 2 C EEPROM. SYS_CLK_IN is in the range of Freescale Semiconductor ...
Page 117
... Reset status register (RSR) • System PLL mode register (SPMR) See Section 4.5, “Memory Map/Register Definitions.” MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor shows how the user should pull down or pull up the reset configuration CFG_RESET_SOURCE[0:3] 0000 (RCW loaded from NOR Flash) 2 ...
Page 118
... RCWLR[LBCM] or RCWLR[DDRCM] or both of them are set. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev SPMF — — Table 4-7. RCWLR Bit Settings Description Section 4.3.2.1.1, “System PLL VCO Division.” for more information. 9 COREPLL Table 4-8, establishes the internal ratio Freescale Semiconductor 15 31 ...
Page 119
... PLL. RCWLR Bits Field Name 4–7 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 4-8. System PLL VCO Division Value Field Name (Binary) ...
Page 120
... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev CORE BMS BOOTSEQ SWEN DIS TSEC2M Description for more information. Access: Read/Write ROMLOC RLEXT — TLE Section 6.2.1, “Arbiter for more information. for more information. Section 4.3.2.2.3, “Boot Freescale Semiconductor 14 15 — — ...
Page 121
... Value RCWHR Bit Field Name (Binary) 5 BMS 0 1 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Description for more information. for more information. for more information. Section 4.3.2.2.6, “e300 Core True Little-Endian,” Table Table 4-11. Boot Memory Space Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF. ...
Page 122
... ROM on the I present. 11 Reserved, should be cleared. NOTE Section 4.3.2.2, “Reset Configuration Word If the e300 core is required to proceed, the boot Section 17.4.5, “Boot Meaning 2 C ROM is accessed interface. A valid ROM must interface. A valid ROM must be Table 4-13, establishes the location of Freescale Semiconductor ...
Page 123
... Word High Register Field Name (RCWHR) Bits 16–18 TSEC1M MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 4-13. Boot ROM Location Legacy Mode (RLEXT = 00) Section 5.1, “Local Memory Map Overview and Example.” Table Table 4-14. eTSEC1 Mode Configuration ...
Page 124
... Reserved 110 Reserved 111 Reserved Table Table 4-16. e300 Core True Little-Endian Value (Binary) 0 Big-endian mode 1 True little-endian mode The following sections describe each of these 4-15, selects the protocol used by the Meaning 4-16, selects whether the e300 core Meaning Freescale Semiconductor ...
Page 125
... The device uses GPCM to load the reset configuration from EEPROM or NOR Flash. The device reads 64 bytes in this case. The local bus controller’s registers setting is set according to MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Bits [8:15] Address 0x00 0x08 ...
Page 126
... C module enters its reset state until HRESET 2 C traffic when the boot sequencer is active. BR0[MSEL] OR0[SCY] 000 1111 001 0010 001 0010 2 C interface. If the device is Section 17.4.5, “Boot Sequencer EEPROM module addresses the 2 C addressing mode, may be Freescale Semiconductor OR0[PGS boot ...
Page 127
... CRC and EEPROM contents, including the preamble, reset configuration words and additional initialization data. In this example assumed that the EEPROM MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Section 4.5.1.1, “Reset Configuration Word Section 4.5.1.2, “Reset Configuration Word High Register ...
Page 128
... DATA[16–23] DATA[24–31 CRC[0–7] CRC[8–15] CRC[16–23] CRC[24–31] Figure 4-6. EEPROM Contents Preamble Reset configuration word low preload command Reset configuration word high preload command Last configuration preload command 0 0 End command Cyclic redundancy check Freescale Semiconductor ...
Page 129
... Comment csb_clk csb_clkx2 Frequency 125 Value 0 Comment csb_clk csb_clkx2 Frequency 133 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor 2 C boot sequencer can be caused by an incorrect EEPROM data RCWLR [0:31] 32'h4504_0000 32'h4404_0000 32'h4405_0000 32'h4406_0000 32'h4406_0000 RCWLR 1 2–3 4–7 SVCOD SPMF RCWLR = 32'h4423_0000 (sysclk = 31 ...
Page 130
... Boot memory space is 0xFF80_0000– 0xFFFF_FFFF. MSR[IP] initial value is 0b1. Boot sequencer is disabled Software watchdog disabled Boot ROM interface location Legacy mode — 000 = MII mode 011 = RGMII mode — Big-endian mode — Freescale Semiconductor ...
Page 131
... Figure 4-7 shows the internal distribution of clocks within the device. 24–66 MHz SYS_CLK_IN USB_CLK_IN SD_REF_CLK SD_REF_CLK + – 100 MHz MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor MPC8308 System Clk PLL Gen ref fb USB PCI Express Protocol Converter PCVTR Mux ...
Page 132
... Default Frequency csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk, csb_clk /2, csb_clk /3 csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk , csb_clk /2, csb_clk /3 csb_clk Off , csb_clk, csb_clk/2, csb_clk/3 NOTE Section 4.3, “Reset Configuration.” Options Freescale Semiconductor ...
Page 133
... Reset Configuration Word Low Register (RCWLR) The reset configuration word low register (RCWLR) is shown in Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR).” MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 4-24. Register Access Reset, Clocking, and Initialization ...
Page 134
... Figure 4-8. Reset Status Register (RSR) Description Section 4.3.1.1, “Reset Configuration Word Source.” boot sequencer has failed while loading the reset Figure 4-4 and described in Access: User read/write SWR — CSHR BMRS Changing this field has no effect. Freescale Semiconductor 14 15 BSF — HRS 0 0 ...
Page 135
... Setting CSRE configures the device to perform a hard reset sequence when the core enters checkstop state. 0 Reset not generated when core enters checkstop state. 1 Reset generated when core enters checkstop state. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Description — All zeros — ...
Page 136
... RCPW All zeros RCPW All zeros Figure 4-10. Reset Protection Register (RPR) Table 4-27. RPR Bit Descriptions Description — All zeros — All zeros Figure 4-11. Reset Control Register (RCR) Access: User read/write 15 31 Access: User read/write SWHR — Freescale Semiconductor ...
Page 137
... Address Reset Configuration—Block Base Address 0x0_0A00 0x0_0A00 System PLL mode register (SPMR) 0x0_0A04 Output clock control register (OCCR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 4-28. RCR Bit Settings Description — All zeros — All zeros Table 4-29. RCER Bit Settings ...
Page 138
... Description Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR)” Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR)” — Section 4.3.2.1.2, “System PLL Configuration” — For more information, see PowerQUICC II Pro MPC8308 Hardware Specification. — Freescale Semiconductor — ...
Page 139
... Reserved, should be cleared 24 LCLK0E Enable/Disable LCLK[0] pin clock out 0 Disable LCLK[0] 1 Enable LCLK[0] 25–31 — Reserved, should be cleared MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor — All zeros 23 — Table 4-32. OCCR Bit Settings Description Reset, Clocking, and Initialization ...
Page 140
... USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR). MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 4-32 Figure 4-15, controls device units that have a NOTE SDHCCM — USBDRCM — Table 4-33. SCCR Bit Descriptions Description Access: Read/Write PCIEXPCM — DMACCM — Freescale Semiconductor ...
Page 141
... DMACCM 00 DMAC core clock is disabled. 01 DMAC core clock/ csb_clk ratio is 1:1. 10 DMAC core clock/ csb_clk ratio is 1:2. 11 DMAC core clock/ csb_clk ratio is 1:3. 28–31 — Reserved MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Reset, Clocking, and Initialization Description 4-33 ...
Page 142
... Reset, Clocking, and Initialization MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 4-34 Freescale Semiconductor ...
Page 143
... Table 5-1. Local Access Windows Target Interface Window Number MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor (PMC)” Target Interface Configuration registers (IMMR) Local bus Local bus Local bus Local bus DDR2 SDRAM DDR2 SDRAM PCI Express Comments Fixed 1-Mbyte window size — ...
Page 144
... Mbytes Unused Location”) and Section 5.1.4.3.1, The local access window, which describes the range of Target Interface DDR2 SDRAM Local bus PCI Express Local bus Configuration registers (IMMR) Local bus boot ROM Flash Section 5.1.4.1, “Internal Memory Map Freescale Semiconductor ...
Page 145
... This window always takes precedence over all local access windows. The IMMRBAR always come out of reset with a default base address value of MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-3. Format of Window Definitions Function ...
Page 146
... Local Access—Block Base Address 0x0_0000 Register A detailed description of the local access Access Reset Section/Page R/W 0xFF40_0000 — — R/W 0x0000_0000 — — 1 R/W 0x0000_0000 2 R/W 0x0000_0000 R/W 0x0000_0000 R/W 0x0000_0000 Freescale Semiconductor 5.1.4.1/5-5 — 5.1.4.2/5-7 — 5.1.4.3/5-7 5.1.4.4/5-8 5.1.4.3/5-7 5.1.4.4/5-8 ...
Page 147
... The internal memory map occupies a 1-Mbyte region of memory space. Its location is programmable using the internal memory map register (IMMR). The default base address for the internal MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Local Access—Block Base Address 0x0_0000 Register Section 5.1.4.3.1, “ ...
Page 148
... Identifies the 12 most-significant address bits of the base of the 1-Mbyte internal memory window. 12–31 — Reserved. Software must write all zeros. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-6 5-2. BASE_ADDR — All zeros Table 5-5. IMMRBAR Bit Settings Description Access: User Read/Write — 31 Freescale Semiconductor ...
Page 149
... Figure 5-4. LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3) 1 The LBLAWBAR0[BASE_ADDR] reset value depends on the reset configuration word high values. See “LBLAWBAR0[BASE_ADDR] Reset Value,” MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor for more information. NOTE Figure 11 12 All zeros Table 5-6 ...
Page 150
... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-8 Description BASE_ADDR Reset Value 0 1 — for a detailed description. for a detailed description. Description 0x00000 0xFF800 Access: Read/Write Section 5.1.4.4.1, “LBLAWAR0[EN] Section 5.1.4.4.1, Freescale Semiconductor Figure 5-5. 31 SIZE ...
Page 151
... Offset 0x80 Reset Figure 5-6. PCI Express 1 Local Access Window Base Address Register (PCIEXP1LAWBAR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor bytes Table 5-10. LBLAWAR0[EN] Reset Value LBLAWAR0[EN] Reset Value 1 e300 core boot not performed from a local bus device. ...
Page 152
... Gbytes 011111–111111 Reserved. Window is undefined. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-10 Table 5-11. PCIEXP1LAWBAR Bit Settings Description — All zeros Table 5-12. PCIEXP1LAWAR Bit Settings Description bytes Figure 5-7. Access: Read/Write 25 26 SIZE (SIZE+1) bytes. Freescale Semiconductor 31 ...
Page 153
... DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-14 defines the reset value DDRLAWBAR0. Table 5-14. DDRLAWBAR0[BASE_ADDR] Reset Value MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor BASE_ADDR 1 All zeros for a detailed description DDRLAWBAR1. ...
Page 154
... ROMLOC field. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-12 — 1,2 All zeros for a detailed description. for a detailed description. Description bytes DDRLAWAR1) are shown in – Access: Read/Write 25 26 SIZE Section 5.1.4.8.1, Section 5.1.4.8.1, (SIZE+1) bytes. (22+1) Freescale Semiconductor 31 ) ...
Page 155
... For instance, the DDR SDRAM controller has chip-select registers that map a memory request to a particular external device. The local bus controller has base registers that perform a similar function. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-16. DDRLAWAR0[EN] Reset Value DDRLAWAR0[EN] ...
Page 156
... Memory Map Registers Base Address Register (IMMRBAR).” IMMRBAR is 0xFF40_0000. The internal memory map window is always the highest priority local access window. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-14 The default value for the NOTE Section 5.1.4.1, Freescale Semiconductor ...
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... PCI Express control register 1 (PECR1) 0x00144 eSDHC control regiser (SDHCCR) 0x00148 RTC control register (RTCCR) 0x00160–0x001FC Reserved 1 Bit #25 depends on the RCW. 2 Bit #30 depend on RCW. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Register Access R/W R/W — R/W R/W R/W — R/W R/W ...
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... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-16 Figure GP All zeros Table 5-19. SGPRL Bit Settings Description Figure GP All zeros Table 5-20. SGPRH Bit Settings Description 5-10, can be used by software for any Access: Read/Write 5-11, can be used by software for Access: Read/Write Freescale Semiconductor 31 31 ...
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... The system priority and configuration register (SPCR), shown in requests for transactions on the internal system bus. This priority is considered by the system arbiter MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor 5-12, provides information about the device and revision numbers. PARTID See ...
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... The level of priority can be chosen from four possible levels. 00 Level 0 (lowest priority) 01 Level 1 10 Level 2 11 Level 3 (highest priority) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev All zeros TSECBDP TSECEP All zeros Table 5-24. SPCR Bit Settings Description Access: Read/Write OPT TBEN COREPR 24 — Freescale Semiconductor 15 — 31 ...
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... TSEC1M field settings in the reset configuration word high in order to select the correct output buffer impedance for full or reduced TSEC pin mode. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-24. SPCR Bit Settings (continued) Description ...
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... Table 5-25. SICRL Bit Settings 0b01 Pin Function 1 — — MSRCID4 MDVAL — — Access: Read/Write UART IRQ_B — — 0b10 0b11 Pin Function 2 Pin Function 3 — — — LSRCID4 — LDVAL — — — — Freescale Semiconductor Reset — 00 ...
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... When SICRL[SPI] = 0b01, SPICLK and SPISEL are in High-Z state. An empty column cannot be used for this register. A function should be selected so that the column is non-empty. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-25. SICRL Bit Settings (continued) 0b01 Pin Function 1 ...
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... Access: Read/Write eSDHC_C GPIO_A USB GTM — — TSOBI1 depends RCW 0b10 0b11 Pin Function 2 Pin Function 3 — GPIO_16 — GPIO_17 — GPIO_18 — GPIO_19 — GPIO_20 — GPIO_21 Freescale Semiconductor GPIO_SEL 0 31 TSOBI2 0 Reset Value 00 00 ...
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... SICRH[Bits] Value Bits Group Pin Function 0 4–5 eSDHC_C 6–7 GPIO_A 8–9 GPIO_B 10–11 IEEE1588_A MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-26. SICRH Bit Settings (continued) 0b00 0b01 Pin Function 1 SD_DAT2 GTM1_TIN2 SD_DAT3 GTM1_TGATE2 GPIO_0 TSEC2_COL GPIO_1 TSEC2_TX_ER ...
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... GPIO_15 — — — GPIO_9 — GPIO_10 2 — GPIO_7 — GPIO_1 — GPIO_2 — GPIO_3 — GPIO_4 2 — GPIO_5 2 — GPIO_6 — GPIO_0 — — Freescale Semiconductor Reset Value — ...
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... If RCWH[ETSEC2M] is RGMII, the reset value is 1; otherwise empty column cannot be used for this register. A function should be selected so that the column is non-empty. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-26. SICRH Bit Settings (continued) 0b00 0b01 Pin Function 1 Reserved — ...
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... Function Selection during Reset LB_POR_CFG_BOOT_ECC CFG_RESET_SOURCE[0] CFG_RESET_SOURCE[1] CFG_RESET_SOURCE[2] CFG_RESET_SOURCE[3] LBC_PM_REF_10 Section 6.2.6, “Arbiter Event Attributes Register 5-16 DSO_NZ — — Normal Operation Mode TSEC1_TX_ER TSEC1_TXD3 TSEC1_TXD2 TSEC1_TXD1 TSEC1_TXD0 TSEC1_TX_EN (AEATR).”). Access: Read/Write DDR_TYPE ODT (Reserved MVREF_SEL M_odr Freescale Semiconductor 15 — — 1 ...
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... DDR SDRAM controller. Offset 0x0012C — Reset Figure 5-17. DDR Debug Status Register (DDRDSR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-28. DDRCDR Field Descriptions Description System Configuration Access: Read — ...
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... LINK_RST CBRST CSR_RST W Reset DEV_TYPE W Reset Figure 5-18. PCI Express Controller Registers (PECR1) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-28 Table 5-29. DDRDSR Field Descriptions Description 3 All zeros — All zeros Access: Read/Write — PRI_DATA PRI_DES PRI_PIO Freescale Semiconductor 15 31 ...
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... Control Registers (SDHCCR) The eSDHC control registers can be used to control various settings that affect the priority and DMA operations. SDHCCR1 is located at offset 0x144. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-30. PECR Field Description Description System Configuration ...
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... Ignore or react to bus errors. 0 React to bus transaction errors 1 Ignore bus transaction errors Reserved Snoop attribute. 0 DMA transactions are not snooped by e300 CPU data cache 1 DMA transactions are snooped by e300 CPU data cache — Access: Read/Write 13 PRIORITY_ — Description Freescale Semiconductor 14 15 CTRL 31 ...
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... Note that individual chapters in this book describe specific initialization aspects for each individual block. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Priority. This field is used to present priority level for CSB arbitration for eSDHC DMA requests. ...
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... If the software watchdog timer is not needed, the user can disable it with software after a system reset. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. • WDT output reset/interrupt mode MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-32 Software Watchdog clock Timer Register Interface Reset or mcp Freescale Semiconductor ...
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... SWTC W Reset SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high). Figure 5-22. System Watchdog Control Register (SWCRR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-33. WDT Register Address Map Register Figure 15 16 System Configuration Access Reset Value Section/ Page — ...
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... Offset 0x8 Reset Figure 5-23. System Watchdog Count Register (SWCNR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-34 Table 5-34. SWCRR Bit Settings Description Figure 15 16 — 5-23, provides visibility to the watchdog Access: Read only SWCN Freescale Semiconductor ...
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... The user should periodically write 0x556C followed by 0xAA39 to this register to prevent a software watchdog timer timeout. SWSRR[WS] can be written at any time, but returns all zeros when read. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-35. SWCNR Bit Settings Description ...
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... Reset Waiting for 0x556C Not 0x556C/Do Not Reload Figure 5-25. Software Watchdog Timer Service State Diagram MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-36 0x556C/Do Not Reload State 0 0xAA39/Reload Not 0xAA39/Do Not Reload Figure 5-25 State 1 Waiting for 0xAA39 Freescale Semiconductor ...
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... WDT reset/interrupt output mode Without software periodic servicing, the software watchdog timer times out and issues a reset or a nonmaskable interrupt (mcp), programmed in SWCRR[SWRI]. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figure 5-26 shows how to handle this need. SWCRR[SWPR] 65,536 ...
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... The RTC can be initialized by software with an initial count value using the real time counter load register (RTLDR). It can also be programmed to generate an interrupt every second. The real time counter control MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-38 must be executed after system reset and not Freescale Semiconductor ...
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... RTC every-second interrupt enable/disable mode • RTC alarm interrupt enable/disable mode • RTC internal/external input clock mode MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Clock Real Time Clock Module Clock Register Interface Figure 5-27. RTC Block Diagram System Configuration ...
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... Table 5-37. RTC External Signals Description Table 5-38. RTC Register Address Map Register Chapter 3, Section/ 1 Access Reset Value Page R/W 0x0000_0000 5.4.6.1/5-41 R/W 0x0000_0000 5.4.6.2/5-42 R/W 0x0000_0000 5.4.6.3/5-42 R 0x0000_0000 5.4.6.4/5-43 w1c 0x0000_0000 5.4.6.5/5-43 R/W 0xFFFF_FFFF 5.4.6.6/5-44 — — Section 5.4.8, “RTC Freescale Semiconductor ...
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... Second interrupt mask bit. Used to enable or disable (mask) the RTC periodic interrupt. 0 Periodic interrupt generation disabled. 1 Periodic interrupt generation enabled. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figure 5-28, is used to enable RTC functions. — All zeros Table 5-39. RTCNR Bit Settings ...
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... CLDV All zeros Table 5-40. RTLDR Bit Settings Description Figure 5-30 read/write register used to PRSC All zeros Table 5-41. RTPSR Bit Settings Description Sequence”) and the loading of a new value into the counter both Access: Read/Write 31 Access: Read/Write 31 Freescale Semiconductor ...
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... Second interrupt flag bit. Used to indicate the every-second interrupt. This status bit is set each time that the prescaler count reaches zero. This bit can be cleared by writing 1. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Figure 5-31 read-only register that shows the CNTV All zeros Table 5-42 ...
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... The RTC function can be disabled by programming the RTC registers. Figure 5-34 shows the functional RTC block diagram. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-44 Figure ALRM Table 5-44. RTALR Bit Settings Description 5-33, contains the 32-bit alarm (ALRM) Access: Read/Write Freescale Semiconductor ...
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... In this mode, the RTC sets the RTEVR[AIF] flag but does not generate an interrupt when the RTC’s 32-bit counter reaches the RTALR[ALR] value. • RTC internal/external input clock mode The input clock to the RTC may be the CSB clock or an external RTC_PIT_CLK. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor RTPSR[PRSC] RTLDR[CLDV] 32-bit 32-bit Prescaler ...
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... The periodic interval timer control register (PTCTR) is used to enable or disable the various timer functions. The periodic interval timer event register (PTEVR) is used to report the interrupt source. The PIT function can be disabled if needed. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-46 Freescale Semiconductor ...
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... Table 5-46. PIT External Signal—Detailed Signal Descriptions Signal I/O RTC_PIT_ I This signal is used as the timebase for the periodic interval timer module. CLOCK MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor PIT Clock Periodic Interval Timer System Clock Register Interface Table 5-45 ...
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... Table 5-48. PTCNR Bit Settings Description Chapter 3, “Memory Map.” Section/ Access Reset Value Page R/W 0x0000_0000 5.5.5.1/5-48 R/W 0x0000_0000 5.5.5.2/5-49 R/W 0x0000_0000 5.5.5.3/5-49 R 0x0000_0000 5.5.5.4/5-50 w1c 0x0000_0000 5.5.5.5/5-50 — — 5-36, is used to enable the different Access: Read/Write CLEN CLIN — Freescale Semiconductor 30 31 PIM ...
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... PIT prescaler’s value. Offset 0x08 Reset Figure 5-38. Periodic Interval Timer Prescale Register (PTPSR) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-48. PTCNR Bit Settings (continued) Description Figure CLDV All zeros Table 5-49. PTLDR Bit Settings Description ...
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... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-50 Table 5-50. PTPSR Bit Settings Description Figure CNTV All zeros Table 5-51. PTCTR Bit Settings Description Figure — All zeros 5-39 read-only register that Access: Read only 5-40, is used to report the source of Access: w1c 30 Freescale Semiconductor 31 31 PIF w1c ...
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... PIT block diagram. PTCNR[CLIN] RTC_PIT _CLOCK Clock Disable System Clocking PTCNR[CLEN] Figure 5-41. Periodic Interval Timer Functional Block Diagram MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-52. PTEVR Bit Settings Description PTPSR[PRSC] PTLDR[CLDV] 32-Bit 32-Bit Prescaler Counter System Configuration PERIODIC ...
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... Each global timer module includes four identical 16-bit general-purpose timers, two 32-bit timers or one 64-bit timer. Each GTM timer consists of a timer prescale register (GTPSR), a timer mode register (GTMDR) a timer capture register (GTCPR), a timer counter register (GTCNR), a timer reference register MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-52 Freescale Semiconductor ...
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... Maximum period of thousands of years (at 125-MHz bus clock and prescaler = 256) for 64-bit timer • 8-nanosecond timer resolution (at 125-MHz bus clock and no prescaler) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor clock Capture Detection Registers Interface Figure 5-42. Global Timers Block Diagram ...
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... The clock input to the timer’s prescaler can be selected from three sources: • The system clock • The system slow go clock (system bus clock internally divided by 16) • The corresponding TINx pin MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-54 Freescale Semiconductor ...
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... Global timer 4 counter gate control signal TOUT1 TOUT1 Global timer 1 counter output signal TOUT2 TOUT2 Global timer 2 counter output signal MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-53. GTM Signal Properties Function System Configuration Require I/O Reset Pull Up ...
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... GTMDR n [ GTMDR n [ICLK n ] bits (GTMDR n [ 1). Thus, TOUT n may be low for one general system clock period, one general system slow go clock period, or one TIN n pin clock cycle period. the timer input clock. Require I/O Reset Pull Freescale Semiconductor ...
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... Timer 2 global timers event register (GTEVR2) 0x034 Timer 3 global timers event register (GTEVR3) 0x036 Timer 4 global timers event register (GTEVR4) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 Freescale Semiconductor Table 5-55. GTM Register Address Map Register System Configuration Reset Section/ Access ...
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... MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0 5-58 Register NOTE STP2 RST2 GM2 All zeros Table 5-56. GTCFR1 Bit Settings Description Reset Section/ Access Value Page R/W 0x0003 5.6.5.7/5-64 Figure 5-43 and Figure 5-44, Access: Read/Write GM1 STP1 RST1 Freescale Semiconductor ...