MPC8308CVMADDA FREESCALE [Freescale Semiconductor, Inc], MPC8308CVMADDA Datasheet
MPC8308CVMADDA
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Freescale Semiconductor MPC8308 PowerQUICC II Pro Processor Hardware Specification This document provides an overview of the MPC8308 features and its hardware specifications, including a block diagram showing the major functional components. The MPC8308 is a cost-effective, low-power, highly integrated host ...
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Electrical Characteristics support. In addition, the MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local bus controller (eLBC), an integrated programmable interrupt controller ...
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Table 1. Absolute Maximum Ratings Characteristic Local bus, DUART, system control and power management, 2 eSDHC USB, Interrupt, Ethernet management, SPI, Miscellaneous and JTAG I/O voltage SERDES PHY eTSEC I/O Voltage Input voltage DDR2 DRAM signals DDR2 DRAM ...
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Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic SerDes analog power for PLL SerDes I/O digital power Core supply voltage Analog supply for e300 core APLL Analog supply for system APLL DDR2 DRAM I/O voltage Differential reference voltage for ...
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Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device G/L/NV + 20% DD G/L/ G/L/ VSS VSS – 0 VSS – 0.7 V Note: 1. Note ...
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Power Characteristics The I/O power supply ramp-up slew rate should be slower than 4V/100 circuit Note that there is no specific power down sequence requirement for the device. I/O voltage supplies ( and not ...
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Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances consume the amount of power described. 1 Table 5. MPC8308 Typical I/O Power Dissipation Interface Parameter DDR2 = 22 Ω bits+ECC s ...
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RESET Initialization 4.2 AC Electrical Characteristics The primary clock source for the device is SYS_CLK_IN. (SYS_CLK_IN) AC timing specifications for the device. Table 8. SYS_CLK_IN AC Timing Specifications Parameter/ SYS_CLK_IN Frequency SYS_CLK_IN Period SYS_CLK_IN Rise and Fall time SYS_CLK_IN Duty ...
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Table 10. RESET Pins DC Electrical Characteristics (continued) Characteristic Output low voltage Output low voltage 5.2 RESET AC Electrical Characteristics Table 11 provides the reset initialization AC timing specifications. Table 11. RESET Initialization Timing Specifications Parameter/Condition Required assertion time of ...
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DDR2 SDRAM 6 DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that DDR2 SDRAM is GV (typ 6.1 DDR2 SDRAM DC Electrical Characteristics Table 13 provides the ...
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Table 15 provides the current draw characteristics for MV Table 15. Current Draw Characteristics for MV Parameter / Condition Current draw for MV REF Note: 1. The voltage regulator for MV 6.2 DDR2 SDRAM AC Electrical Characteristics This section provides ...
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DDR2 SDRAM Figure 4 illustrates the DDR2 input timing diagram showing the t MCK[n] MCK[n] MDQS[n] MDQ[x]/ MECC[x] 6.2.2 DDR2 SDRAM Output AC Timing Specifications Table 18. DDR2 SDRAM Output AC Timing Specifications Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD ...
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Table 18. DDR2 SDRAM Output AC Timing Specifications (continued) Parameter MDQS preamble start MDQS epilogue end Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) (DD) from ...
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DUART Figure 6 shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram Figure 7 provides the AC test load for the DDR2 bus. Output 7 DUART This ...
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Table 19. DUART DC Electrical Characteristics (continued) Parameter Low-level output voltage Input current (0 V ≤V ≤ 7.2 DUART AC Electrical Specifications Table 20 provides the AC timing parameters for the DUART interface. Parameter Minimum baud ...
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Ethernet: Three-Speed Ethernet, MII Management 8.1.1 eTSEC DC Electrical Characteristics All MII and RGMII drivers and receivers comply with the DC parametric attributes specified in and Table 22. The RGMII signals are based on a 2.5-V CMOS interface voltage as ...
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MII Transmit AC Timing Specifications Table 23 provides the MII transmit AC timing specifications. Table 23. MII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK ...
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Ethernet: Three-Speed Ethernet, MII Management Table 24. MII Receive AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise V (min (max RX_CLK clock fall ...
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Table 25. RGMII AC Timing Specifications (continued) At recommended operating conditions with LV 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) GTX_CLK125 reference clock period GTX_CLK125 ...
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Ethernet: Three-Speed Ethernet, MII Management 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII and RGMII are specified ...
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Table 27. MII Management AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition MDC fall time Notes: 1. The symbols used for timing specifications Follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) ...
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USB Table 28. GPIO DC Electrical Characteristics (continued) Characteristic Input low voltage Input current 8.4.2 IEEE 1588 Timer AC Specifications Table 29 provides the IEEE 1588 timer AC specifications. Table 29. IEEE 1588 Timer AC Specifications Parameter Timer clock cycle ...
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USB AC Electrical Specifications Table 31 lists the general timing parameters of the USB-ULPI interface. Parameter USB clock cycle time Input setup to USB clock—all inputs Input hold to USB clock—all inputs USB clock to output valid—all outputs Output ...
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High-Speed Serial Interfaces (HSSI) 10 High-Speed Serial Interfaces (HSSI) This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also ...
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Common Mode Voltage, V The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output )/2 ...
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High-Speed Serial Interfaces (HSSI) • The supply voltage requirements for XCOREVDD are specified in • SerDes reference clock receiver reference circuit structure — The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 16. Each differential clock ...
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DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described ...
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High-Speed Serial Interfaces (HSSI) 200 mV < Input Amplitude or Differential Peak < 800mV SD_REF_CLK SD_REF_CLK Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200mV < Input Amplitude or Differential Peak < 800mV SD_REF_CLK SD_REF_CLK Figure 18. Differential ...
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Figure 20 to Figure 23 fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers very possible that the clock circuit reference designs provided by clock driver chip ...
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High-Speed Serial Interfaces (HSSI) Figure 21 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8308’s SerDes reference clock input’s allowed range (100 to 400 ...
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Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8308 SerDes reference clock input’s DC requirement, AC-coupling has to ...
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High-Speed Serial Interfaces (HSSI) Figure 23 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock input’s DC requirement. Single-Ended ...
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Table 32. SerDes Reference Clock AC Parameters (continued) At recommended operating conditions with XCOREVDD= 1.0V ± 5% Parameter Rising edge rate (SD_REF_CLK) to falling edge rate (SD_REF_CLK) matching Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from ...
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PCI Express 10.2.4.1 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 10.3 SerDes Transmitter and Receiver Reference Circuits Figure 26 shows the reference circuits for SerDes ...
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Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock ...
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PCI Express Table 34. Differential Transmitter (TX) Output Specifications (continued) Parameter Symbol D+/D- TX output rise/fall T TX-RISE time T TX-FALL RMS AC peak common V TX-CM-ACp mode output voltage Absolute delta TX-CM-DC- common mode voltage ACTIVE- ...
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Table 34. Differential Transmitter (TX) Output Specifications (continued) Parameter Symbol Maximum time to T TX-IDLE-SET-TO-I transition to a valid DLE electrical idle after sending an electrical idle ordered set Maximum time to T TX-IDLE-TO-DIFF- transition to valid TX DATA specifications ...
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PCI Express Table 34. Differential Transmitter (TX) Output Specifications (continued) Parameter Symbol Crosslink random timeout T crosslink Notes test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance ...
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V (D+ D– Crossing Point) Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications 11.4.3 Differential Receiver (RX) Input Specifications Table 35 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the ...
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PCI Express Table 35. Differential Receiver (RX) Input Specifications (continued) Parameter Symbol Maximum time between T RX-EYE-MEDIAN-t the jitter median and o-MAX-JITTER maximum deviation from the median. AC peak common mode V RX-CM-ACp input voltage Differential return loss RL RX-DIFF ...
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Table 35. Differential Receiver (RX) Input Specifications (continued) Parameter Symbol Total Skew L RX-SKEW Notes test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test ...
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PCI Express and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI ...
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Figure 29. Compliance Test/Measurement Load 12 Enhanced Local Bus This section describes the DC and AC electrical specifications for the enhanced local bus interface. 12.1 Enhanced Local Bus DC Electrical Characteristics Table 36 provides the DC electrical characteristics for the ...
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Enhanced Local Bus Table 37. Local Bus General Timing Parameters (continued) Parameter Local bus clock to output valid (Note revisited) Local bus clock to output high impedance for LD (Note revisited) Notes: 1. The symbols used ...
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Figure 31 through Figure 33 show the local bus signals. In what follows, T1,T2,T3,T4 are internal clock reference phase signals corresponding to LCCR[CLKDIV]. LCLK0 Input Signals: LD[0:15] Input Signal: LGTA t Output Signals: LBCTL//LOE/ Output Signals: LA[0:25] Figure 31. Local ...
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Enhanced Local Bus LCLK0 T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8308 PowerQUICC II Pro Processor ...
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LCLK GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV Enhanced Secure Digital Host Controller ...
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Enhanced Secure Digital Host Controller (eSDHC) Table 38. eSDHC interface DC Electrical Characteristics (continued) Characteristic Output low voltage Input high voltage Input low voltage 13.2 eSDHC AC Timing Specifications (Full Speed Mode) This section describes the AC electrical specifications for ...
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Figure 34 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 34. eSDHC Clock Input Timing Diagram 13.2.1 Full Speed Output Path (Write) Figure 35 provides the data and command output timing diagram. SD CLK at ...
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Enhanced Secure Digital Host Controller (eSDHC) 13.2.2 Full Speed Input Path (Read) Figure 36 provides the data and command input timing diagram. SD CLK at the MPC8308 Pin SD CLK at the Card Pin Output from the SD Card Pins ...
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Table 40. eSDHC AC Timing Specifications for High Speed Mode (continued) At recommended operating conditions NV DD Parameter SD Card Output Valid SD Card Output Hold Note: 1 The symbols used for timing specifications herein follow the pattern of t ...
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Enhanced Secure Digital Host Controller (eSDHC) 13.3.1 High Speed Output Path (Write) Figure 38 provides the data and command output timing diagram. SD CLK at the MPC8308 Pin SD CLK at the Card Pin Output Valid Time: t Output Hold ...
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JTAG This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface. 14.1 JTAG DC Electrical Characteristics Table 41 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 41. JTAG Interface ...
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JTAG Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) At recommended operating conditions (see Parameter Output hold times: Boundary-scan data JTAG external clock to output high impedance: Boundary-scan data Notes: 1. All outputs are measured from the midpoint voltage ...
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Figure 42 provides the TRST timing diagram. TRST Figure 43 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs Figure 44 provides the test access port timing ...
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This section describes the DC and AC electrical characteristics for the Electrical Characteristics Table 43 provides the DC electrical characteristics for the I At recommended operating conditions ...
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Table 44. I All values refer to V (min) and V (max) levels (see IH IL Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device ...
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Timers 16 Timers This section describes the DC and AC electrical specifications for the timers. 16.1 Timers DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, TOUT, and TGATE. Table 45. Timers ...
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GPIO This section describes the DC and AC electrical specifications for the GPIO of MPC8308 17.1 GPIO DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the GPIO. Characteristic Output high voltage Output low voltage Output low ...
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IPIC 18 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins. 18.1 IPIC DC Electrical Characteristics Table 49 provides the DC electrical characteristics for the external interrupt pins. Characteristic Input high voltage Input low ...
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Table 51. SPI DC Electrical Characteristics (continued) Characteristic Output high voltage Output low voltage Output low voltage 19.2 SPI AC Timing Specifications Table 52 and provide the SPI input and output AC timing specifications. Characteristic SPI outputs valid—master mode (internal ...
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Package and Pin Listings Figure 50 shows the SPI timing in slave mode (external clock). SPICLK (input) t NEIVKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 50. SPI ...
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Mechanical Dimensions of the MPC8308 MAPBGA Figure 52 shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package. Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG Notes: 1. All dimensions are in millimeters. ...
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Package and Pin Listings 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 20.3 Pinout Listings ...
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Table 53. MPC8308 Pinout Listing (continued) Signal MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] MEMC_MDQ[31] MEMC_MDM[0] MEMC_MDM[1] MEMC_MDM[2] MEMC_MDM[3] MEMC_MDM[8] MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MDQS[8] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MWE ...
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Package and Pin Listings Table 53. MPC8308 Pinout Listing (continued) Signal MEMC_MCAS MEMC_MCS[0] MEMC_MCS[1] MEMC_MCKE MEMC_MCK [0] MEMC_MCK [1] MEMC_MCK [2] MEMC_MCK [0] MEMC_MCK [1] MEMC_MCK [2] MEMC_MODT[0] MEMC_MODT[1] MEMC_MECC[0] MEMC_MECC[1] MEMC_MECC[2] MEMC_MECC[3] MEMC_MECC[4] MEMC_MECC[5] MEMC_MECC[6] MEMC_MECC[7] MV REF LD0 ...
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Table 53. MPC8308 Pinout Listing (continued) Signal LD11 LD12 LD13 LD14 LD15 LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LCS[0] LCS[1] ...
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Package and Pin Listings Table 53. MPC8308 Pinout Listing (continued) Signal LCS[3] LWE[0] /LFWE0/LBS0 LWE[1]/LBS1 LBCTL LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 UART_SOUT1/MSRCID0/LSRCID0 UART_SIN1/MSRCID1/LSRCID1 UART_SOUT2/MSRCID2/LSRCID2 UART_SIN2/MSRCID3/LSRCID3 TXA TXA RXA RXA SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SD_PLL_TPA_ANA SDAVDD_0 SDAVSS_0 IIC_SDA1 ...
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Table 53. MPC8308 Pinout Listing (continued) Signal IIC_SDA2/CKSTOP_OUT IIC_SCL2/CKSTOP_IN IRQ[0]/MCP_IN IRQ[1]/MCP_OUT IRQ[2] /CKSTOP_OUT IRQ[3] /CKSTOP_IN TCK TDI TDO TMS TRST TEST_MODE HRESET PORESET SRESET SYS_CLK_IN RTC_PIT_CLOCK QUIESCE THERM0 TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RXD[3] MPC8308 PowerQUICC II Pro Processor Hardware ...
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Package and Pin Listings Table 53. MPC8308 Pinout Listing (continued) Signal TSEC1_RXD[2] TSEC1_RXD[1] TSEC1_RXD[0] TSEC1_RX_ER TSEC1_TX_CLK/TSEC1_GTX_CLK125 TSEC1_TXD[3]/CFG_RESET_SOURCE[0] TSEC1_TXD[2]/CFG_RESET_SOURCE[1] TSEC1_TXD[1]/CFG_RESET_SOURCE[2] TSEC1_TXD[0]/CFG_RESET_SOURCE[3] TSEC1_TX_EN/LBC_PM_REF_10 TSEC1_TX_ER/LB_POR_CFG_BOOT_ECC TSEC1_MDC TSEC1_MDIO SD_CLK/GPIO_16 SD_CMD/GPIO_17 SD_CD/GTM1_TIN1/GPIO_18 SD_WP/GTM1_TGATE1/GPIO_19 SD_DAT[0]/GTM1_TOUT1/GPIO_20 SD_DAT[1]/GTM1_TOUT2/GPIO_21 SD_DAT[2]/GTM1_TIN2/GPIO_22 SD_DAT[3]/GTM1_TGATE2/GPIO_23 SPIMOSI/MSRCID4/LSRCID4 SPIMISO/MDVAL/LDVAL SPICLK SPISEL GPIO[0]/TSEC2_COL GPIO[1]/TSEC2_TX_ER GPIO[2]/TSEC2_GTX_CLK GPIO[3]/TSEC2_RX_CLK ...
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Table 53. MPC8308 Pinout Listing (continued) Signal GPIO[4]/TSEC2_RX_DV GPIO[5]/TSEC2_RXD3 GPIO[6]/TSEC2_RXD2 GPIO[7]/TSEC2_RXD1 GPIO[8]/TSEC2_RXD0 GPIO[9]/TSEC2_RX_ER GPIO[10]/TSEC2_TX_CLK/TSEC2_GTX_CLK125 GPIO[11]/TSEC2_TXD3 GPIO[12]/TSEC2_TXD2 GPIO[13]/TSEC2_TXD1 GPIO[14]/TSEC2_TXD0 GPIO[15]/TSEC2_TX_EN USBDR_PWR_FAULT USBDR_CLK USBDR_DIR USBDR_NXT USBDR_TXDRXD0 USBDR_TXDRXD1 USBDR_TXDRXD2 USBDR_TXDRXD3 USBDR_TXDRXD4 USBDR_TXDRXD5 USBDR_TXDRXD6 USBDR_TXDRXD7 USBDR_PCTL0 USBDR_PCTL1 USBDR_STP TSEC_TMR_CLK/ GPIO[8] GTM1_TOUT3/ GPIO[9] GTM1_TOUT4/ GPIO[10] ...
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Package and Pin Listings Table 53. MPC8308 Pinout Listing (continued) Signal TSEC_TMR_PP1 TSEC_TMR_PP2 TSEC_TMR_PP3/ GPIO[13] TSEC_TMR_ALARM1 TSEC_TMR_ALARM2/ GPIO[14] GPIO[7] TSEC2_CRS TSEC1_TMR_RX_ESFD/ GPIO[1] TSEC1_TMR_TX_ESFD/GPIO[2] TSEC0_TMR_RX_ESFD/GPIO[3] TSEC0_TMR_TX_ESFD/ GPIO[4] GTM1_TGATE3 GTM1_TIN4 GTM1_TGATE4/ GPIO[15] GTM1_TIN3 GPIO[5] GPIO[6] AV DD1 AV DD2 NC, No Connection ...
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Table 53. MPC8308 Pinout Listing (continued) Signal VSS NV DDA NV DDB NV DDC NV DDF NV DDG NV DDH NV DDJ NV DDP_K GV DD XPADVDD XPADVSS MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0 Freescale Semiconductor Package ...
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Package and Pin Listings Table 53. MPC8308 Pinout Listing (continued) Signal XCOREVDD XCOREVSS Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin This pin is ...
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Clocking Figure 53 shows the internal distribution of clocks within the device. 24–66 MHz SYS_CLK_IN eSHDC SD_CLK SD_REF_CLK SD_REF_CLK_B + PLL - 125/100 MHz 1 Multiplication factor 1.5, 2, 2.5, and 3. Value is decided by ...
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Clocking 21.1 System Clock Domains The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop (PLL) and the clock unit to create three major clock domains: • The coherent system bus clock (csb_clk) • The internal ...
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Table 55 provides the operating frequencies for the device under recommended operating conditions (Table 2). Table 55. Operating Frequencies for MPC8308 Characteristic e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) 2 DDR2 memory bus frequency (MCK) 3 Local bus ...
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Clocking coherent system bus clock (csb_clk). for select csb_clk to SYS_CLK_IN ratios. SPMF csb_clk :Input Clock Ratio 0010 0100 0101 21.3 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core ...
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Table 58. e300 Core PLL Configuration (continued) RCWL[COREPLL] 0–1 2– 0010 1 00 0011 0 01 0011 0 10 0011 0 Note: 1 For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 333 ...
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Thermal Table 59. Package Thermal Characteristics for MAPBGA (continued) Characteristic Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on ...
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At a known board temperature, the junction temperature is estimated using the following equation: ...
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System Design Information 23.1 System Clocking The device includes two PLLs. 1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input. The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio ...
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These decoupling capacitors should receive their power from separate V V power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed SS directly under the device using a standard escape pattern. Others may surround the ...
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System Design Information The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The ...
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Pull-Up Resistor Requirements The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins 2 including I C, Ethernet management MDIO, HRESET and IPIC (integrated programmable interrupt controller). Correct operation of the JTAG interface ...
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Document Revision History 24.2 Part Marking Parts are marked as in the example shown in Figure 56. Freescale Part Marking for PBGA Devices Table 62 shows the SVR settings: Device MPC8308 Note: PVR = 8085_0020 for the device. 25 Document ...
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THIS PAGE INTENTIONALLY LEFT BLANK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0 Freescale Semiconductor Document Revision History 87 ...
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