MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 961

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 16-54
16.5.3.6
This section describes the MIB registers. The eTSEC RMON module has separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB.
An interrupt can be generated upon any one counter’s rollover condition through a carry interrupt output
from the RMON. Each counter’s rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
Freescale Semiconductor
16–31
8–15
0–7
Bit
Exact Match Address, 2nd Octet
Exact Match Address, 1st Octet
describes the fields of a MACxADDR2 register.
MIB Registers
RMON counters do not comprehend custom VLAN tagged frames.
Affected counters include TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO,
RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF. Specifically,
custom VLAN tagged frames are not afforded the ability to be greater than
1518, as compared to the IEEE standard tagged frames.
The transmit and receive frame counters (TR64, TR127, TR 255, TR511,
TR1K, TRMAX, adn TRMGV) do not increment for aborted frames
(collision retry limit exceeded, late collision, underrun, EBERR, TxFIFO
data error, frame truncated due to exceeding MAXFRM, or excessive
deferral).
Table 16-54. MAC01ADDR2–MAC15ADDR2 Field Descriptions
Name
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
—
octet (destination address bits 8–15) defaults to a value of 0x0.
(destination address bits 0–7) defaults to a value of 0x0.
Reserved
This field holds the second octet of the exact match address. The second
This field holds the first octet of the exact match address. The first octet
NOTE
NOTE
Description
Enhanced Three-Speed Ethernet Controllers
16-77