MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 256

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

e300 Processor Core Overview
Table 7-4
7-24
22–23
29–30
Bits
21
24
25
26
27
28
31
DECAREN
NOOPTI
shows how HID0[ECLK] and HID0[SBCLK] are used to configure the clk_out signal.
FBIOB
Name
IFEM
DCFI
ABE
—
—
—
Asserted
Negated
hreset
Table 7-4. Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out
Data cache Flash invalidate
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins (usually
1 An invalidate operation is issued that marks the state of each data cache block as invalid without
For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive
mtspr operations.
Reserved, should be cleared.
Enable M bit on bus for instruction fetches
0 M bit not reflected on bus for instruction fetches. Instruction fetches are treated as nonglobal on the
1 Instruction fetches reflect the M bit from the WIM settings
Decrementer auto reload
0 Normal operation.
1 Decrementer loads last mtdec value for precise periodic interrupt.
Reserved, should be cleared.
Force branch indirect on the bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally
Address broadcast enable. Controls whether certain address-only operations (such as cache
operations) are broadcast on the bus.
0 Address-only operations affect only local caches and are not broadcast
1 Address-only operations are broadcast on the bus
Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts
are not snooped by the e300 core. Refer to Section 4.3.3, “Data Cache Control,” for more information.
Reserved, should be cleared.
No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled
1 The dcbt and dcbtst instructions are no-oped internal to the e300 core
the next cycle after the write operation to the register). The data cache must be enabled for the
invalidation to occur.
writing back modified cache blocks to memory. Cache access is blocked during this time. Bus
accesses to the cache are signaled as a miss during invalidate-all operations. Setting DCFI clears all
the valid bits of the blocks and the PLRU bits to point to way L0 of each set.
bus.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
ECLK
x
0
0
1
1
Table 7-3. e300 HID0 Bit Descriptions (continued)
SBCLK
0
1
0
1
x
Bus clock (small pulse for every rising edge of sysclk)
Clock output off
Core clock/2
Core clock
Bus clock
Function
clk_out
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