MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 504

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
Figure 11-12
Table 11-14
11-24
Offset: 0x030 (IRQSTAT)
Reset
Reset
0–2
4–6
Bit
10
3
7
8
9
W
W
R
R
16
0
AC12E
DMAE
describes the IRQSTAT fields.
Name
DEBE
DCE
shows the interrupt status register.
—
—
—
—
2
Reserved
DMA error. Occurs when internal DMA transfer failed. This bit is set when some error occurs in the
data transfer. The value in the DMA system address register is the next fetch address where the error
occurs. Since any error corrupts the entire data block, the host driver should restart the transfer from
the corrupted block boundary. The address of the block boundary can be calculated from the current
DS_ADDR value or the remaining number of blocks and the block size.
0 No Error
1 Error
Reserved
Auto CMD12 error. Occurs when one of the bits in AUTOC12ERR is set. This bit is also set when Auto
CMD12 is not executed due to a previous command error.
0 No Error
1 Error
Reserved
Data end bit error. Occurs when detecting 0 at the end bit position of read data on the SD_DAT line or
at the end bit position of the CRC.
0 No Error
1 Error
Note: When DEBE and CINT are set, the software should ignore DEBE. But, it must not ignore the
Data CRC error. Occurs when detecting CRC error when transferring read data on the SD_DAT line
or when detecting the write CRC status having a value other than 0b010.
0 No Error
1 Error
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
DMAE
w1c
other status bits. The software should also clear this bit by writing 1 to it. It is highly
recommended to clear this bit before the next transfer.
—
3
Figure 11-12. Interrupt Status Register (IRQSTAT)
Table 11-14. IRQSTAT Field Descriptions
4
—
22
6
AC12E
CINT
w1c
w1c
23
7
All zeros
All zeros
CRM CINS BRR
w1c
—
24
Description
8
DEBE DCE DTOE
w1c
w1c
25
9
w1c
w1c
10
26
BWR DINT BGE
w1c
w1c
11
27
w1c
w1c
CIE
12
28
Freescale Semiconductor
CEBE
w1c
w1c
13
29
CCE
w1c
w1c
TC
Access: w1c
14
30
CTOE
w1c
w1c
CC
15
31