MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 876

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCAL
Quantity:
300
Part Number:
MPC8308VMAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCALE
Quantity:
6
Part Number:
MPC8308VMAGD
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC8308VMAGD
Quantity:
2 000
Part Number:
MPC8308VMAGD400/266
Manufacturer:
FREESCAL
Quantity:
300
Part Number:
MPC8308VMAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8308VMAGDA
Quantity:
4 200
SerDes PHY
15.3.1
SRDSCR0, shown in
Table 15-3
15-4
4–15
Offset 0x000
Reset
Reset
Bits
2–3
16
0
1
W
W
R
R
TLCCA
DPPA
RXEQA Receive equalization selection bus for lane A—when asserted in PCI Express mode:
TLCCA
Name
DPPA
16
0
1
0
defines the bit fields of SRDSCR0.
SerDes Control Register 0 (SRDSCR0)
17
0
1
1
Tracking loop centering control for lane A. When enabled, it centers the first-stage digital filter after the
second-stage filter moves transition point.
0 Enable recentering algorithm
1 Disable recentering algorithm
Recommended setting per protocol is PCI Express: 0
Reserved
00 No equalization
01 2 dB of equalization
10 4 dB of equalization
11 Reserved
Reserved
Diff pk-pk swing for lane A. Sets the peak value for output swing of transmitters and the amount of transmit
equalization for lane A.
0 V
1 Reserved
Recommended setting per protocol is PCI Express: 0
TXEQA
RXEQA
DD-diff-pk-pk
0
0
2
Figure
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
1
1
19
1
0
3
Figure 15-2. SerDes Control Register 0 (SRDSCR0)
15-2, contains the functional control bits for the SerDes logic.
20
0
1
4
Table 15-3. SRDSCR0 Field Descriptions
0
1
0
0
23
1
0
SDPD
24
0
0
Description
25
0
0
IACCA
26
0
1
27
0
1
0
0
Freescale Semiconductor
29
0
0
Access: Read/write
RXEIA
30
0
0
15
31
0
0

Related parts for MPC8308VMAGD