MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 779

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.4.4.9
The PCI Express device capabilities register is shown in
of these fields can be set indirectly, using the PCI Express Device Capabilities Update Register. See
Section 14.4.6.9, “PCI Express Device Capabilities Update Register (PEX_DEVCAP_UPDATE),”
additional details.
Table 14-47
Freescale Semiconductor
31–28
27–26
25–18
17–15
Offset 0x050
Reset
Reset
11–9
Bits
Bits
7–4
3–0
8–6
14
13
12
5
W
W
R
R
—
31
15
0
0
EP_L0s_LAT
EP_L1_LAT
Device/Port Type
describes the PCI Express capabilities register fields.
PCI Express Device Capabilities Register
CSPLS
CSPLV
PIP
Table 14-46. PCI Express Capabilities Register Fields Description (continued)
Name
14
0
0
ABP
PIP
AIP
ET
—
—
Version
Table 14-47. PCI Express Device Capabilities Register Fields Description
Name
—
AIP
13
0
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 14-49. PCI Express Device Capabilities Register
ABP
28
12
0
0
Reserved
Captured slot power limit scale
Captured slot power limit value
Reserved
Power indicator present
Attention indicator present
Attention button present
Endpoint L1 acceptable latency
Endpoint L0s acceptable latency
Extended tag field supported
0100 (RC mode)
0000 (EP mode)
Indicates PCI-SIG defined PCI Express capability structure version number.
0x1identifies version 1.0a.
27
11
0
0
CSPLS
EP_L1_LAT
26
0
0
25
0
0
9
0
0
8
EP_L0s_LAT
Figure
0
0
Description
14-49. Note that for End Point mode some
Description
0
6
0
CSPLV
ET
0
0
5
PHAN_FCT
0
0
4
PCI Express Interface Controller
0
0
3
MAX_PL_SIZE_SUP
18
0
0
2
Access: Read-only
17
0
0
—
for
14-41
16
0
0
0