MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 520

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
only restriction is from the external card since it may not support such a large block or a partial block
access that is not an integer multiple of 512 bytes.
11.5.1.4
This SDIO command CMD53 definition limits the maximum data size of data transfers according to the
following formula:
The length of a multiple block transfer must be in block size units. If the total data length cannot be divided
evenly to a multiple of the block size, then there are two ways to transfer the data depending on the function
and card design.
See
size of up to 4096 bytes, the example below illustrates a maximum of 64 bytes where the data must be
divided.
11.5.2
The internal DMA implements a DMA engine and CSB master. When the internal DMA is enabled
(XFERTYP[DMAEN] is set), the buffer interrupt status bits are still set if they are enabled. To avoid
setting them, clear IRQSTATEN[BWRSEN, BRRSEN]. See
CSB interface block. The internal DMA must not be used to read (or write) data if the data will be written
(or read) by the CPU through the DATPORT register.
11-40
544-bytes WLAN Frame
WLAN Frame is divided equally into 64-byte blocks plus the remainder 32-bytes
Eight 64-byte blocks are sent in Block Transfer Mode and the remainder
32-bytes are sent in Byte Transfer Mode
•
•
Figure 11-21
CMD53
The card driver splits the transaction. The remainder of block size data is then transferred using a
single block command at the end.
Add dummy data in the last block to fill the block size. The card must remove the dummy data.
DMA CSB Interface
Dividing Large Data Transfer
MAC Header
for an example of dividing large data transfers. Although the eSDHC supports a block
SDIO Data
SDIO Data
64-bytes
Block 1
Block 1
802.11
Data
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Maximum data size = (block size) × (block count)
Figure 11-21. Example of Dividing a Large Data Transfer
IV
SDIO Data
SDIO Data
64-bytes
Block 2
Block 2
Data
Frame Body
• • •
• • •
• • •
Figure 11-22
SDIO Data
SDIO Data
64-bytes
Block 8
Block 8
Data
for illustration of the DMA
ICV
SDIO Data
32-bytes
32-bytes
Freescale Semiconductor
CMD53
Data
FCS
SDIO Data
32-bytes
Eqn. 11-2