MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 329

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other
chip selects’ bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_BNDS are used, and all fields in CS1_BNDS are unused.
CSn_BNDS are shown in
Table 9-6
9.4.1.2
The chip select configuration (CSn_CONFIG) registers shown in
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the
other registers’ fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields.
Freescale Semiconductor
Offset 0x000, 0x008
Reset
16–23
24–31
8–15
Bits
0–7
W
R
0
Name
SA n
EA n
describes the CSn_BNDS register fields.
—
—
Chip Select Configuration (CS n _CONFIG)
Reserved
Starting address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
Reserved
Ending address for chip select (bank) n. This value is compared against the 8 msbs of the 32-bit address.
—
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 9-2. Chip Select Bounds Registers (CS n _BNDS)
Figure
7
8
Table 9-6. CS n_ BNDS Field Descriptions
9-2.
SA n
All zeros
15 16
Description
Figure 9-3
—
enable the DDR chip selects
23 24
DDR Memory Controller
Access: Read/Write
EA n
9-11
31