MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1087

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5.8.1
In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt
routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode. A dummy read of
I2CDR then releases SCL so that the master can generate a STOP condition. See
17.5.8.2
When a master loses arbitration the following conditions all occur:
Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear it if it is
set. See
Freescale Semiconductor
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•
•
I2CSR[MAL] is set
I2CCR[MSTA] is cleared (changing the master to slave mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Section 17.4.2.1, “Arbitration Control.”
Slave Transmitter and Received Acknowledge
Loss of Arbitration and Forcing of Slave Mode
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure
17-11.
I
2
C Interface
17-25