MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1085

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5.2
A hard reset initializes all of the I
initializes the I
17.5.3
After initialization, the following sequence can be used to generate START:
The scenario above assumes that the I
an I
17.5.4
Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]), which
indicates that one byte has been transferred. The I
is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CCR[MIEN] is set). In the interrupt handler, software must take the following steps:
If the interrupt function is disabled, software can service the I2CDR in the main program by monitoring
I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF] because MCF behaves
differently when arbitration is lost. Note that interrupt or other bus conditions may be detected before the
I
may be needed to give the I
Freescale Semiconductor
2
C signals have time to settle. Thus, when polling I2CSR[MIF] (or any other I2CSR bits), software delays
1. All I
2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the
3. Update I2CADR to define the slave address for this device.
4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
5. Set the I2CCR[MEN] to enable the I
1. If the device is connected to a multimaster I
2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode (set
3. Write the slave address being called into I2CDR. The data written to I2CDR[0–6] forms the slave
2
1. Clear I2CSR[MIF]
2. Read the I2CDR in receive mode or write to I2CDR in transmit mode. Note that this causes
3. When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If
C interrupt is generated (provided interrupt reporting is enabled with I2CCR[MIEN] =1).
CSB (platform) clock.
disable.
(I2CSR[MBB] = 0) before switching to master mode.
I2CCR[MTX]) for the address cycle.
calling address. I2CCR[MTX] indicates the direction of transfer (transmit/receive) required from
the slave.
I2CSR[MCF] to be cleared, as shown in
master receive mode is required, I2CCR[MTX] must be toggled at this stage (see
Initialization Sequence
Generation of START
Post-Transfer Software Response
2
C registers must be located in a cache-inhibited page.
2
C unit:
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
2
C signals sufficient time to settle.
2
C registers to their default states. The following initialization sequence
2
C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any time,
2
C interface.
Figure
2
C interrupt bit (I2CSR[MIF]) is also set and an interrupt
2
C system, check whether the serial bus is free
17-11.
Figure
I
2
C Interface
17-11).
17-23