MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 609

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
BSEIS
BSVIS
ASVIS
AVVIE
AVVIS
Name
1msS
1msT
DPIS
DPS
IDIE
IDIS
BSE
BSV
ASV
AVV
—
—
A VBus valid interrupt enable
1 Enable
0 Disable
USB ID interrupt enable.
1 Enable
0 Disable
Reserved, should be cleared.
Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only
detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0).
Software must write a one to clear this bit.
1-millisecond timer interrupt status. Set once every millisecond.
Software must write a one to clear this bit.
B session end interrupt status. Set when VBus has fallen below the B session end threshold.
Software must write a one to clear this bit.
B session valid interrupt status. Set when VBus has either risen above or fallen below the B session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
A session valid interrupt status. Set when VBus has either risen above or fallen below the A session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
A VBus valid interrupt status. Set when VBus has either risen above or fallen below the VBus valid threshold
(4.4 VDC) on an A device.
Software must write a one to clear this bit.
USB ID interrupt status. Set when a change on the ID input has been detected.
Software must write a one to clear this bit.
Reserved, should be cleared.
Data bus pulsing status
1 Pulsing detected on port
0 No pulsing on port
1 millisecond timer toggle. This bit toggles once per millisecond.
B session end
1 VBus is below the B session end threshold.
0 VBus is above the B session end threshold.
B session valid
1 VBus is above the B session valid threshold.
0 VBus is below the B session valid threshold.
A session valid
1 VBus is above the A session valid threshold.
0 VBus is below the A session valid threshold.
A VBus valid
1 VBus is above the A VBus valid threshold.
0 VBus is below the A VBus valid threshold.
Table 13-24. OTGSC Register Field Descriptions (continued)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Description
Universal Serial Bus Interface
13-31