MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1144

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Complete List of Configuration, Control, and Status Registers
A.13 DDR Memory Controller
A-8
0x150–0xBF4 Reserved
0x140–0x144 Reserved
Offset
0x00C
0x008
0x010
0x014
0xBFC
Offset
0x10C
0x11C
0xBF8
0xE00
0xE04
0xE08
0x000
0x008
0x080
0x084
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x148
GPIO data register (GPDAT)
GPIO interrupt event register (GPIER)
GPIO interrupt mask register (GPIMR)
GPIO external interrupt control register (GPICR)
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
DDR_INIT_ADDR—DDR training initialization address
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
DATA_ERR_INJECT_HI—Memory data path error injection mask
high
DATA_ERR_INJECT_LO—Memory data path error injection mask
low
ERR_INJECT—Memory data path error injection mask ECC
Table A-12. General Purpose I/O (GPIO) Registers (continued)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
General Purpose I/O (GPIO)—Block Base Address 0x0_0C00
DDR Memory Controller—Block Base Address 0x0_2000
Table A-13. DDR Memory Controller Registers
Register
Register
Access
R/W
R/W
R/W
w1c
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
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R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x nnnn _ nnnn
0x00 nn _00 nn
Undefined
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Reset
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